diff options
| -rw-r--r-- | src/mesa/drivers/dri/i915/Makefile.sources | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/i830_vtbl.c | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/i915_vtbl.c | 9 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_blit.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_context.c | 8 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_context.h | 20 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_fbo.c | 76 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_fbo.h | 34 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_mipmap_tree.c | 222 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_mipmap_tree.h | 116 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_resolve_map.c | 111 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_resolve_map.h | 104 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i915/intel_screen.c | 6 |
13 files changed, 4 insertions, 716 deletions
diff --git a/src/mesa/drivers/dri/i915/Makefile.sources b/src/mesa/drivers/dri/i915/Makefile.sources index 350683bd66e..243da9b44c1 100644 --- a/src/mesa/drivers/dri/i915/Makefile.sources +++ b/src/mesa/drivers/dri/i915/Makefile.sources @@ -15,7 +15,6 @@ i915_FILES = \ intel_clear.c \ intel_extensions.c \ intel_mipmap_tree.c \ - intel_resolve_map.c \ intel_tex_layout.c \ intel_tex_image.c \ intel_tex_subimage.c \ diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c b/src/mesa/drivers/dri/i915/i830_vtbl.c index b30f45edfa8..500edac5ec4 100644 --- a/src/mesa/drivers/dri/i915/i830_vtbl.c +++ b/src/mesa/drivers/dri/i915/i830_vtbl.c @@ -878,12 +878,6 @@ i830_invalidate_state(struct intel_context *intel, GLuint new_state) i830_update_provoking_vertex(&intel->ctx); } -static bool -i830_is_hiz_depth_format(struct intel_context *intel, gl_format format) -{ - return false; -} - void i830InitVtbl(struct i830_context *i830) { @@ -901,5 +895,4 @@ i830InitVtbl(struct i830_context *i830) i830->intel.vtbl.finish_batch = intel_finish_vb; i830->intel.vtbl.invalidate_state = i830_invalidate_state; i830->intel.vtbl.render_target_supported = i830_render_target_supported; - i830->intel.vtbl.is_hiz_depth_format = i830_is_hiz_depth_format; } diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 91fde5587f9..5f6e249357d 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -847,14 +847,6 @@ i915_assert_not_dirty( struct intel_context *intel ) (void) dirty; } -/** Return false; i915 does not support HiZ. */ -static bool -i915_is_hiz_depth_format(struct intel_context *intel, - gl_format format) -{ - return false; -} - static void i915_invalidate_state(struct intel_context *intel, GLuint new_state) { @@ -882,5 +874,4 @@ i915InitVtbl(struct i915_context *i915) i915->intel.vtbl.finish_batch = intel_finish_vb; i915->intel.vtbl.invalidate_state = i915_invalidate_state; i915->intel.vtbl.render_target_supported = i915_render_target_supported; - i915->intel.vtbl.is_hiz_depth_format = i915_is_hiz_depth_format; } diff --git a/src/mesa/drivers/dri/i915/intel_blit.c b/src/mesa/drivers/dri/i915/intel_blit.c index da56f55c4df..90796bce187 100644 --- a/src/mesa/drivers/dri/i915/intel_blit.c +++ b/src/mesa/drivers/dri/i915/intel_blit.c @@ -205,11 +205,9 @@ intel_miptree_blit(struct intel_context *intel, return false; } - /* The blitter has no idea about HiZ or fast color clears, so we need to - * resolve the miptrees before we do anything. + /* The blitter has no idea about fast color clears, so we need to resolve + * the miptrees before we do anything. */ - intel_miptree_slice_resolve_depth(intel, src_mt, src_level, src_slice); - intel_miptree_slice_resolve_depth(intel, dst_mt, dst_level, dst_slice); intel_miptree_resolve_color(intel, src_mt); intel_miptree_resolve_color(intel, dst_mt); diff --git a/src/mesa/drivers/dri/i915/intel_context.c b/src/mesa/drivers/dri/i915/intel_context.c index 23d8281b4ca..26cef1149b8 100644 --- a/src/mesa/drivers/dri/i915/intel_context.c +++ b/src/mesa/drivers/dri/i915/intel_context.c @@ -544,7 +544,6 @@ intelInitContext(struct intel_context *intel, intel->has_separate_stencil = intel->intelScreen->hw_has_separate_stencil; intel->must_use_separate_stencil = intel->intelScreen->hw_must_use_separate_stencil; - intel->has_hiz = intel->gen >= 6; intel->has_llc = intel->intelScreen->hw_has_llc; intel->has_swizzling = intel->intelScreen->hw_has_swizzling; @@ -663,13 +662,6 @@ intelInitContext(struct intel_context *intel, intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z"); - if (!driQueryOptionb(&intel->optionCache, "hiz")) { - intel->has_hiz = false; - /* On gen6, you can only do separate stencil with HIZ. */ - if (intel->gen == 6) - intel->has_separate_stencil = false; - } - intel->prim.primitive = ~0; /* Force all software fallbacks */ diff --git a/src/mesa/drivers/dri/i915/intel_context.h b/src/mesa/drivers/dri/i915/intel_context.h index eac65ba5423..566950351bb 100644 --- a/src/mesa/drivers/dri/i915/intel_context.h +++ b/src/mesa/drivers/dri/i915/intel_context.h @@ -182,10 +182,6 @@ struct intel_context bool (*render_target_supported)(struct intel_context *intel, struct gl_renderbuffer *rb); - /** Can HiZ be enabled on a depthbuffer of the given format? */ - bool (*is_hiz_depth_format)(struct intel_context *intel, - gl_format format); - /** * Surface state operations (i965+ only) * \{ @@ -207,21 +203,6 @@ struct intel_context uint32_t *out_offset, bool dword_pitch); /** \} */ - - /** - * Send the appropriate state packets to configure depth, stencil, and - * HiZ buffers (i965+ only) - */ - void (*emit_depth_stencil_hiz)(struct brw_context *brw, - struct intel_mipmap_tree *depth_mt, - uint32_t depth_offset, - uint32_t depthbuffer_format, - uint32_t depth_surface_type, - struct intel_mipmap_tree *stencil_mt, - bool hiz, bool separate_stencil, - uint32_t width, uint32_t height, - uint32_t tile_x, uint32_t tile_y); - } vtbl; GLbitfield Fallback; /**< mask of INTEL_FALLBACK_x bits */ @@ -242,7 +223,6 @@ struct intel_context bool is_945; bool has_separate_stencil; bool must_use_separate_stencil; - bool has_hiz; bool has_llc; bool has_swizzling; diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c b/src/mesa/drivers/dri/i915/intel_fbo.c index d16523bbbf6..655e14c0a48 100644 --- a/src/mesa/drivers/dri/i915/intel_fbo.c +++ b/src/mesa/drivers/dri/i915/intel_fbo.c @@ -490,13 +490,6 @@ intel_renderbuffer_update_wrapper(struct intel_context *intel, intel_renderbuffer_set_draw_offset(irb); - if (mt->hiz_mt == NULL && - intel->vtbl.is_hiz_depth_format(intel, rb->Format)) { - intel_miptree_alloc_hiz(intel, mt); - if (!mt->hiz_mt) - return false; - } - return true; } @@ -650,16 +643,6 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) "instead of S8\n", _mesa_get_format_name(stencil_mt->format)); } - if (intel->gen < 7 && !intel_renderbuffer_has_hiz(depthRb)) { - /* Before Gen7, separate depth and stencil buffers can be used - * only if HiZ is enabled. From the Sandybridge PRM, Volume 2, - * Part 1, Bit 3DSTATE_DEPTH_BUFFER.SeparateStencilBufferEnable: - * [DevSNB]: This field must be set to the same value (enabled - * or disabled) as Hierarchical Depth Buffer Enable. - */ - fbo_incomplete(fb, "FBO incomplete: separate stencil " - "without HiZ\n"); - } } } @@ -840,61 +823,6 @@ intel_renderbuffer_set_needs_downsample(struct intel_renderbuffer *irb) irb->mt->need_downsample = true; } -/** - * Does the renderbuffer have hiz enabled? - */ -bool -intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb) -{ - return intel_miptree_slice_has_hiz(irb->mt, irb->mt_level, irb->mt_layer); -} - -void -intel_renderbuffer_set_needs_hiz_resolve(struct intel_renderbuffer *irb) -{ - if (irb->mt) { - intel_miptree_slice_set_needs_hiz_resolve(irb->mt, - irb->mt_level, - irb->mt_layer); - } -} - -void -intel_renderbuffer_set_needs_depth_resolve(struct intel_renderbuffer *irb) -{ - if (irb->mt) { - intel_miptree_slice_set_needs_depth_resolve(irb->mt, - irb->mt_level, - irb->mt_layer); - } -} - -bool -intel_renderbuffer_resolve_hiz(struct intel_context *intel, - struct intel_renderbuffer *irb) -{ - if (irb->mt) - return intel_miptree_slice_resolve_hiz(intel, - irb->mt, - irb->mt_level, - irb->mt_layer); - - return false; -} - -bool -intel_renderbuffer_resolve_depth(struct intel_context *intel, - struct intel_renderbuffer *irb) -{ - if (irb->mt) - return intel_miptree_slice_resolve_depth(intel, - irb->mt, - irb->mt_level, - irb->mt_layer); - - return false; -} - void intel_renderbuffer_move_to_temp(struct intel_context *intel, struct intel_renderbuffer *irb, @@ -916,10 +844,6 @@ intel_renderbuffer_move_to_temp(struct intel_context *intel, irb->mt->num_samples, INTEL_MIPTREE_TILING_ANY); - if (intel->vtbl.is_hiz_depth_format(intel, new_mt->format)) { - intel_miptree_alloc_hiz(intel, new_mt); - } - intel_miptree_copy_teximage(intel, intel_image, new_mt, invalidate); intel_miptree_reference(&irb->mt, intel_image->mt); diff --git a/src/mesa/drivers/dri/i915/intel_fbo.h b/src/mesa/drivers/dri/i915/intel_fbo.h index e1b4df567db..af94185ce58 100644 --- a/src/mesa/drivers/dri/i915/intel_fbo.h +++ b/src/mesa/drivers/dri/i915/intel_fbo.h @@ -164,40 +164,6 @@ intel_get_rb_region(struct gl_framebuffer *fb, GLuint attIndex); void intel_renderbuffer_set_needs_downsample(struct intel_renderbuffer *irb); -bool -intel_renderbuffer_has_hiz(struct intel_renderbuffer *irb); - -void -intel_renderbuffer_set_needs_hiz_resolve(struct intel_renderbuffer *irb); - -void -intel_renderbuffer_set_needs_depth_resolve(struct intel_renderbuffer *irb); - - -/** - * \brief Perform a HiZ resolve on the renderbuffer. - * - * It is safe to call this function on a renderbuffer without HiZ. In that - * case, the function is a no-op. - * - * \return false if no resolve was needed - */ -bool -intel_renderbuffer_resolve_hiz(struct intel_context *intel, - struct intel_renderbuffer *irb); - -/** - * \brief Perform a depth resolve on the renderbuffer. - * - * It is safe to call this function on a renderbuffer without HiZ. In that - * case, the function is a no-op. - * - * \return false if no resolve was needed - */ -bool -intel_renderbuffer_resolve_depth(struct intel_context *intel, - struct intel_renderbuffer *irb); - void intel_renderbuffer_move_to_temp(struct intel_context *intel, struct intel_renderbuffer *irb, bool invalidate); diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c index 058cfbe1bcc..766b1b9c6f1 100644 --- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.c @@ -33,7 +33,6 @@ #include "intel_context.h" #include "intel_mipmap_tree.h" #include "intel_regions.h" -#include "intel_resolve_map.h" #include "intel_tex_layout.h" #include "intel_tex.h" #include "intel_blit.h" @@ -376,9 +375,7 @@ intel_miptree_create_layout(struct intel_context *intel, if (!for_bo && _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL && - (intel->must_use_separate_stencil || - (intel->has_separate_stencil && - intel->vtbl.is_hiz_depth_format(intel, format)))) { + (intel->must_use_separate_stencil)) { mt->stencil_mt = intel_miptree_create(intel, mt->target, MESA_FORMAT_S8, @@ -763,12 +760,6 @@ intel_miptree_create_for_renderbuffer(struct intel_context *intel, if (!mt) goto fail; - if (intel->vtbl.is_hiz_depth_format(intel, format)) { - ok = intel_miptree_alloc_hiz(intel, mt); - if (!ok) - goto fail; - } - if (mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) { ok = intel_miptree_alloc_mcs(intel, mt, num_samples); if (!ok) @@ -814,12 +805,10 @@ intel_miptree_release(struct intel_mipmap_tree **mt) intel_region_release(&((*mt)->region)); intel_miptree_release(&(*mt)->stencil_mt); - intel_miptree_release(&(*mt)->hiz_mt); #ifndef I915 intel_miptree_release(&(*mt)->mcs_mt); #endif intel_miptree_release(&(*mt)->singlesample_mt); - intel_resolve_map_clear(&(*mt)->hiz_map); for (i = 0; i < MAX_TEXTURE_LEVELS; i++) { free((*mt)->level[i].slice); @@ -1270,210 +1259,6 @@ intel_miptree_alloc_non_msrt_mcs(struct intel_context *intel, #endif } - -/** - * Helper for intel_miptree_alloc_hiz() that sets - * \c mt->level[level].slice[layer].has_hiz. Return true if and only if - * \c has_hiz was set. - */ -static bool -intel_miptree_slice_enable_hiz(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) -{ - assert(mt->hiz_mt); - - if (intel->is_haswell) { - /* Disable HiZ for some slices to work around a hardware bug. - * - * Haswell hardware fails to respect - * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y when during HiZ - * ambiguate operations. The failure is inconsistent and affected by - * other GPU contexts. Running a heavy GPU workload in a separate - * process causes the failure rate to drop to nearly 0. - * - * To workaround the bug, we enable HiZ only when we can guarantee that - * the Depth Coordinate Offset fields will be set to 0. The function - * brw_get_depthstencil_tile_masks() is used to calculate the fields, - * and the function is sometimes called in such a way that the presence - * of an attached stencil buffer changes the fuction's return value. - * - * The largest tile size considered by brw_get_depthstencil_tile_masks() - * is that of the stencil buffer. Therefore, if this hiz slice's - * corresponding depth slice has an offset that is aligned to the - * stencil buffer tile size, 64x64 pixels, then - * 3DSTATE_DEPTH_BUFFER.Depth_Coordinate_Offset_X/Y is set to 0. - */ - uint32_t depth_x_offset = mt->level[level].slice[layer].x_offset; - uint32_t depth_y_offset = mt->level[level].slice[layer].y_offset; - if ((depth_x_offset & 63) || (depth_y_offset & 63)) { - return false; - } - } - - mt->level[level].slice[layer].has_hiz = true; - return true; -} - - - -bool -intel_miptree_alloc_hiz(struct intel_context *intel, - struct intel_mipmap_tree *mt) -{ - assert(mt->hiz_mt == NULL); - mt->hiz_mt = intel_miptree_create(intel, - mt->target, - mt->format, - mt->first_level, - mt->last_level, - mt->logical_width0, - mt->logical_height0, - mt->logical_depth0, - true, - mt->num_samples, - INTEL_MIPTREE_TILING_ANY); - - if (!mt->hiz_mt) - return false; - - /* Mark that all slices need a HiZ resolve. */ - struct intel_resolve_map *head = &mt->hiz_map; - for (int level = mt->first_level; level <= mt->last_level; ++level) { - for (int layer = 0; layer < mt->level[level].depth; ++layer) { - if (!intel_miptree_slice_enable_hiz(intel, mt, level, layer)) - continue; - - head->next = malloc(sizeof(*head->next)); - head->next->prev = head; - head->next->next = NULL; - head = head->next; - - head->level = level; - head->layer = layer; - head->need = GEN6_HIZ_OP_HIZ_RESOLVE; - } - } - - return true; -} - -/** - * Does the miptree slice have hiz enabled? - */ -bool -intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) -{ - intel_miptree_check_level_layer(mt, level, layer); - return mt->level[level].slice[layer].has_hiz; -} - -void -intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) -{ - if (!intel_miptree_slice_has_hiz(mt, level, layer)) - return; - - intel_resolve_map_set(&mt->hiz_map, - level, layer, GEN6_HIZ_OP_HIZ_RESOLVE); -} - - -void -intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) -{ - if (!intel_miptree_slice_has_hiz(mt, level, layer)) - return; - - intel_resolve_map_set(&mt->hiz_map, - level, layer, GEN6_HIZ_OP_DEPTH_RESOLVE); -} - -static bool -intel_miptree_slice_resolve(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer, - enum gen6_hiz_op need) -{ - intel_miptree_check_level_layer(mt, level, layer); - - struct intel_resolve_map *item = - intel_resolve_map_get(&mt->hiz_map, level, layer); - - if (!item || item->need != need) - return false; - - intel_hiz_exec(intel, mt, level, layer, need); - intel_resolve_map_remove(item); - return true; -} - -bool -intel_miptree_slice_resolve_hiz(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) -{ - return intel_miptree_slice_resolve(intel, mt, level, layer, - GEN6_HIZ_OP_HIZ_RESOLVE); -} - -bool -intel_miptree_slice_resolve_depth(struct intel_context *intel, - struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer) -{ - return intel_miptree_slice_resolve(intel, mt, level, layer, - GEN6_HIZ_OP_DEPTH_RESOLVE); -} - -static bool -intel_miptree_all_slices_resolve(struct intel_context *intel, - struct intel_mipmap_tree *mt, - enum gen6_hiz_op need) -{ - bool did_resolve = false; - struct intel_resolve_map *i, *next; - - for (i = mt->hiz_map.next; i; i = next) { - next = i->next; - if (i->need != need) - continue; - - intel_hiz_exec(intel, mt, i->level, i->layer, need); - intel_resolve_map_remove(i); - did_resolve = true; - } - - return did_resolve; -} - -bool -intel_miptree_all_slices_resolve_hiz(struct intel_context *intel, - struct intel_mipmap_tree *mt) -{ - return intel_miptree_all_slices_resolve(intel, mt, - GEN6_HIZ_OP_HIZ_RESOLVE); -} - -bool -intel_miptree_all_slices_resolve_depth(struct intel_context *intel, - struct intel_mipmap_tree *mt) -{ - return intel_miptree_all_slices_resolve(intel, mt, - GEN6_HIZ_OP_DEPTH_RESOLVE); -} - - void intel_miptree_resolve_color(struct intel_context *intel, struct intel_mipmap_tree *mt) @@ -2159,11 +1944,6 @@ intel_miptree_map_singlesample(struct intel_context *intel, return; } - intel_miptree_slice_resolve_depth(intel, mt, level, slice); - if (map->mode & GL_MAP_WRITE_BIT) { - intel_miptree_slice_set_needs_hiz_resolve(mt, level, slice); - } - if (mt->format == MESA_FORMAT_S8) { intel_miptree_map_s8(intel, mt, map, level, slice); } else if (mt->etc_format != MESA_FORMAT_NONE && diff --git a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h index 6dab092c8f3..1e43bbecb06 100644 --- a/src/mesa/drivers/dri/i915/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i915/intel_mipmap_tree.h @@ -31,7 +31,6 @@ #include <assert.h> #include "intel_regions.h" -#include "intel_resolve_map.h" #ifdef __cplusplus extern "C" { @@ -63,7 +62,6 @@ extern "C" { * temporary system buffers. */ -struct intel_resolve_map; struct intel_texture_image; /** @@ -152,15 +150,6 @@ struct intel_mipmap_level * intel_miptree_map/unmap on this slice. */ struct intel_miptree_map *map; - - /** - * \brief Is HiZ enabled for this slice? - * - * If \c mt->level[l].slice[s].has_hiz is set, then (1) \c mt->hiz_mt - * has been allocated and (2) the HiZ memory corresponding to this slice - * resides at \c mt->hiz_mt->level[l].slice[s]. - */ - bool has_hiz; } *slice; }; @@ -346,11 +335,6 @@ struct intel_mipmap_tree GLuint total_width; GLuint total_height; - /* The 3DSTATE_CLEAR_PARAMS value associated with the last depth clear to - * this depth mipmap tree, if any. - */ - uint32_t depth_clear_value; - /* Includes image offset tables: */ struct intel_mipmap_level level[MAX_TEXTURE_LEVELS]; @@ -408,28 +392,6 @@ struct intel_mipmap_tree bool need_downsample; /** - * \brief HiZ miptree - * - * The hiz miptree contains the miptree's hiz buffer. To allocate the hiz - * miptree, use intel_miptree_alloc_hiz(). - * - * To determine if hiz is enabled, do not check this pointer. Instead, use - * intel_miptree_slice_has_hiz(). - */ - struct intel_mipmap_tree *hiz_mt; - - /** - * \brief Map of miptree slices to needed resolves. - * - * This is used only when the miptree has a child HiZ miptree. - * - * Let \c mt be a depth miptree with HiZ enabled. Then the resolve map is - * \c mt->hiz_map. The resolve map of the child HiZ miptree, \c - * mt->hiz_mt->hiz_map, is unused. - */ - struct intel_resolve_map hiz_map; - - /** * \brief Stencil miptree for depthstencil textures. * * This miptree is used for depthstencil textures and renderbuffers that @@ -631,70 +593,6 @@ intel_miptree_alloc_mcs(struct intel_context *intel, struct intel_mipmap_tree *mt, GLuint num_samples); -/** - * \name Miptree HiZ functions - * \{ - * - * It is safe to call the "slice_set_need_resolve" and "slice_resolve" - * functions on a miptree without HiZ. In that case, each function is a no-op. - */ - -/** - * \brief Allocate the miptree's embedded HiZ miptree. - * \see intel_mipmap_tree:hiz_mt - * \return false if allocation failed - */ - -bool -intel_miptree_alloc_hiz(struct intel_context *intel, - struct intel_mipmap_tree *mt); - -bool -intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t layer); - -void -intel_miptree_slice_set_needs_hiz_resolve(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t depth); -void -intel_miptree_slice_set_needs_depth_resolve(struct intel_mipmap_tree *mt, - uint32_t level, - uint32_t depth); - -/** - * \return false if no resolve was needed - */ -bool -intel_miptree_slice_resolve_hiz(struct intel_context *intel, - struct intel_mipmap_tree *mt, - unsigned int level, - unsigned int depth); - -/** - * \return false if no resolve was needed - */ -bool -intel_miptree_slice_resolve_depth(struct intel_context *intel, - struct intel_mipmap_tree *mt, - unsigned int level, - unsigned int depth); - -/** - * \return false if no resolve was needed - */ -bool -intel_miptree_all_slices_resolve_hiz(struct intel_context *intel, - struct intel_mipmap_tree *mt); - -/** - * \return false if no resolve was needed - */ -bool -intel_miptree_all_slices_resolve_depth(struct intel_context *intel, - struct intel_mipmap_tree *mt); - /**\}*/ /** @@ -766,20 +664,6 @@ intel_miptree_unmap(struct intel_context *intel, unsigned int level, unsigned int slice); -#ifdef I915 -static inline void -intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op) -{ - /* Stub on i915. It would be nice if we didn't execute resolve code at all - * there. - */ -} -#else -void -intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt, - unsigned int level, unsigned int layer, enum gen6_hiz_op op); -#endif #ifdef __cplusplus } diff --git a/src/mesa/drivers/dri/i915/intel_resolve_map.c b/src/mesa/drivers/dri/i915/intel_resolve_map.c deleted file mode 100644 index 04b5c942432..00000000000 --- a/src/mesa/drivers/dri/i915/intel_resolve_map.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright © 2011 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#include "intel_resolve_map.h" - -#include <assert.h> -#include <stdlib.h> - -/** - * \brief Set that the miptree slice at (level, layer) needs a resolve. - * - * If a map element already exists with the given key, then the value is - * changed to the given value of \c need. - */ -void -intel_resolve_map_set(struct intel_resolve_map *head, - uint32_t level, - uint32_t layer, - enum gen6_hiz_op need) -{ - struct intel_resolve_map **tail = &head->next; - struct intel_resolve_map *prev = head; - - while (*tail) { - if ((*tail)->level == level && (*tail)->layer == layer) { - (*tail)->need = need; - return; - } - prev = *tail; - tail = &(*tail)->next; - } - - *tail = malloc(sizeof(**tail)); - (*tail)->prev = prev; - (*tail)->next = NULL; - (*tail)->level = level; - (*tail)->layer = layer; - (*tail)->need = need; -} - -/** - * \brief Get an element from the map. - * \return null if element is not contained in map. - */ -struct intel_resolve_map* -intel_resolve_map_get(struct intel_resolve_map *head, - uint32_t level, - uint32_t layer) -{ - struct intel_resolve_map *item = head->next; - - while (item) { - if (item->level == level && item->layer == layer) - break; - else - item = item->next; - } - - return item; -} - -/** - * \brief Remove and free an element from the map. - */ -void -intel_resolve_map_remove(struct intel_resolve_map *elem) -{ - if (elem->prev) - elem->prev->next = elem->next; - if (elem->next) - elem->next->prev = elem->prev; - free(elem); -} - -/** - * \brief Remove and free all elements of the map. - */ -void -intel_resolve_map_clear(struct intel_resolve_map *head) -{ - struct intel_resolve_map *next = head->next; - struct intel_resolve_map *trash; - - while (next) { - trash = next; - next = next->next; - free(trash); - } - - head->next = NULL; -} diff --git a/src/mesa/drivers/dri/i915/intel_resolve_map.h b/src/mesa/drivers/dri/i915/intel_resolve_map.h deleted file mode 100644 index 8504271f5cb..00000000000 --- a/src/mesa/drivers/dri/i915/intel_resolve_map.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright © 2011 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#pragma once - -#include <stdint.h> - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * For an overview of the HiZ operations, see the following sections of the - * Sandy Bridge PRM, Volume 1, Part2: - * - 7.5.3.1 Depth Buffer Clear - * - 7.5.3.2 Depth Buffer Resolve - * - 7.5.3.3 Hierarchical Depth Buffer Resolve - * - * Of these, two get entered in the resolve map as needing to be done to the - * buffer: depth resolve and hiz resolve. - */ -enum gen6_hiz_op { - GEN6_HIZ_OP_DEPTH_CLEAR, - GEN6_HIZ_OP_DEPTH_RESOLVE, - GEN6_HIZ_OP_HIZ_RESOLVE, - GEN6_HIZ_OP_NONE, -}; - -/** - * \brief Map of miptree slices to needed resolves. - * - * The map is implemented as a linear doubly-linked list. - * - * In the intel_resolve_map*() functions, the \c head argument is not - * inspected for its data. It only serves as an anchor for the list. - * - * \par Design Discussion - * - * There are two possible ways to record which miptree slices need - * resolves. 1) Maintain a flag for every miptree slice in the texture, - * likely in intel_mipmap_level::slice, or 2) maintain a list of only - * those slices that need a resolve. - * - * Immediately before drawing, a full depth resolve performed on each - * enabled depth texture. If design 1 were chosen, then at each draw call - * it would be necessary to iterate over each miptree slice of each - * enabled depth texture in order to query if each slice needed a resolve. - * In the worst case, this would require 2^16 iterations: 16 texture - * units, 16 miplevels, and 256 depth layers (assuming maximums for OpenGL - * 2.1). - * - * By choosing design 2, the number of iterations is exactly the minimum - * necessary. - */ -struct intel_resolve_map { - uint32_t level; - uint32_t layer; - enum gen6_hiz_op need; - - struct intel_resolve_map *next; - struct intel_resolve_map *prev; -}; - -void -intel_resolve_map_set(struct intel_resolve_map *head, - uint32_t level, - uint32_t layer, - enum gen6_hiz_op need); - -struct intel_resolve_map* -intel_resolve_map_get(struct intel_resolve_map *head, - uint32_t level, - uint32_t layer); - -void -intel_resolve_map_remove(struct intel_resolve_map *elem); - -void -intel_resolve_map_clear(struct intel_resolve_map *head); - -#ifdef __cplusplus -} /* extern "C" */ -#endif - diff --git a/src/mesa/drivers/dri/i915/intel_screen.c b/src/mesa/drivers/dri/i915/intel_screen.c index 60a69a60648..31526ace84c 100644 --- a/src/mesa/drivers/dri/i915/intel_screen.c +++ b/src/mesa/drivers/dri/i915/intel_screen.c @@ -54,10 +54,6 @@ PUBLIC const char __driConfigOptions[] = DRI_CONF_DESC_END DRI_CONF_OPT_END - DRI_CONF_OPT_BEGIN_B(hiz, "true") - DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+") - DRI_CONF_OPT_END - DRI_CONF_OPT_BEGIN_B(early_z, "false") DRI_CONF_DESC(en, "Enable early Z in classic mode (unstable, 945-only).") DRI_CONF_OPT_END @@ -82,7 +78,7 @@ PUBLIC const char __driConfigOptions[] = DRI_CONF_SECTION_END DRI_CONF_END; -const GLuint __driNConfigOptions = 14; +const GLuint __driNConfigOptions = 13; #include "intel_batchbuffer.h" #include "intel_buffers.h" |