diff options
60 files changed, 976 insertions, 1636 deletions
diff --git a/Makefile.am b/Makefile.am index a9ed31ee123..6e24dd5e5a7 100644 --- a/Makefile.am +++ b/Makefile.am @@ -51,7 +51,6 @@ noinst_HEADERS = \ include/c99_alloca.h \ include/c99_compat.h \ include/c99_math.h \ - include/c99 \ include/c11 \ include/D3D9 \ include/HaikuGL \ diff --git a/configure.ac b/configure.ac index e3d721d93aa..acfca57a400 100644 --- a/configure.ac +++ b/configure.ac @@ -305,8 +305,7 @@ if test "x$GCC" = xyes; then # Flags to help ensure that certain portions of the code -- and only those # portions -- can be built with MSVC: - # - src/util, src/gallium/auxiliary, and src/gallium/drivers/llvmpipe needs - # to build with Windows SDK 7.0.7600, which bundles MSVC 2008 + # - src/util, src/gallium/auxiliary, rc/gallium/drivers/llvmpipe, and # - non-Linux/Posix OpenGL portions needs to build on MSVC 2013 (which # supports most of C99) # - the rest has no compiler compiler restrictions @@ -323,9 +322,6 @@ if test "x$GCC" = xyes; then AC_MSG_RESULT([yes])], AC_MSG_RESULT([no])); CFLAGS="$save_CFLAGS" - - MSVC2008_COMPAT_CFLAGS="$MSVC2013_COMPAT_CFLAGS -Werror=declaration-after-statement" - MSVC2008_COMPAT_CXXFLAGS="$MSVC2013_COMPAT_CXXFLAGS" fi if test "x$GXX" = xyes; then CXXFLAGS="$CXXFLAGS -Wall" @@ -353,8 +349,6 @@ fi AC_SUBST([MSVC2013_COMPAT_CFLAGS]) AC_SUBST([MSVC2013_COMPAT_CXXFLAGS]) -AC_SUBST([MSVC2008_COMPAT_CFLAGS]) -AC_SUBST([MSVC2008_COMPAT_CXXFLAGS]) dnl even if the compiler appears to support it, using visibility attributes isn't dnl going to do anything useful currently on cygwin apart from emit lots of warnings @@ -2188,7 +2182,7 @@ radeon_llvm_check() { if test "x$enable_gallium_llvm" != "xyes"; then AC_MSG_ERROR([--enable-gallium-llvm is required when building $1]) fi - llvm_check_version_for "3" "5" "0" $1 + llvm_check_version_for "3" "6" "0" $1 if test true && $LLVM_CONFIG --targets-built | grep -iqvw $amdgpu_llvm_target_name ; then AC_MSG_ERROR([LLVM $amdgpu_llvm_target_name not enabled in your LLVM build.]) fi diff --git a/docs/index.html b/docs/index.html index 2b1e64673ac..8c13a0a5b3e 100644 --- a/docs/index.html +++ b/docs/index.html @@ -16,6 +16,12 @@ <h1>News</h1> +<h2>February 10, 2016</h2> +<p> +<a href="relnotes/11.1.2.html">Mesa 11.1.2</a> is released. +This is a bug-fix release. +</p> + <h2>January 22, 2016</h2> <p> <a href="relnotes/11.0.9.html">Mesa 11.0.9</a> is released. diff --git a/docs/relnotes.html b/docs/relnotes.html index 2f527a428f7..90fdf9287b0 100644 --- a/docs/relnotes.html +++ b/docs/relnotes.html @@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each Mesa release. </p> <ul> +<li><a href="relnotes/11.1.2.html">11.1.2 release notes</a> <li><a href="relnotes/11.0.9.html">11.0.9 release notes</a> <li><a href="relnotes/11.1.1.html">11.1.1 release notes</a> <li><a href="relnotes/11.0.8.html">11.0.8 release notes</a> diff --git a/docs/relnotes/11.1.2.html b/docs/relnotes/11.1.2.html new file mode 100644 index 00000000000..43938a62f63 --- /dev/null +++ b/docs/relnotes/11.1.2.html @@ -0,0 +1,182 @@ +<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd"> +<html lang="en"> +<head> + <meta http-equiv="content-type" content="text/html; charset=utf-8"> + <title>Mesa Release Notes</title> + <link rel="stylesheet" type="text/css" href="../mesa.css"> +</head> +<body> + +<div class="header"> + <h1>The Mesa 3D Graphics Library</h1> +</div> + +<iframe src="../contents.html"></iframe> +<div class="content"> + +<h1>Mesa 11.1.2 Release Notes / February 10, 2016</h1> + +<p> +Mesa 11.1.2 is a bug fix release which fixes bugs found since the 11.1.1 release. +</p> +<p> +Mesa 11.1.2 implements the OpenGL 4.1 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.1. OpenGL +4.1 is <strong>only</strong> available if requested at context creation +because compatibility contexts are not supported. +</p> + + +<h2>SHA256 checksums</h2> +<pre> +ba0e7462b2936b86e6684c26fbb55519f8d9ad31d13a1c1e1afbe41e73466eea mesa-11.1.2.tar.gz +8f72aead896b340ba0f7a4a474bfaf71681f5d675592aec1cb7ba698e319148b mesa-11.1.2.tar.xz +</pre> + + +<h2>New features</h2> +<p>None</p> + +<h2>Bug fixes</h2> + +<p>This list is likely incomplete.</p> + +<ul> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=91596">Bug 91596</a> - EGL_KHR_gl_colorspace (v2) causes problem with Android-x86 GUI</li> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93628">Bug 93628</a> - Exception: attempt to use unavailable module DRM when building MesaGL 11.1.0 on windows</li> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93648">Bug 93648</a> - Random lines being rendered when playing Dolphin (geometry shaders related, w/ apitrace)</li> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93650">Bug 93650</a> - GL_ARB_separate_shader_objects is buggy (PCSX2)</li> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93717">Bug 93717</a> - Meta mipmap generation can corrupt texture state</li> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93722">Bug 93722</a> - Segfault when compiling shader with a subroutine that takes a parameter</li> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93731">Bug 93731</a> - glUniformSubroutinesuiv segfaults when subroutine uniform is bound to a specific location</li> + +<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=93761">Bug 93761</a> - A conditional discard in a fragment shader causes no depth writing at all</li> + +</ul> + + +<h2>Changes</h2> + +<p>Ben Widawsky (1):</p> +<ul> + <li>i965/bxt: Fix conservative wm thread counts.</li> +</ul> + +<p>Dave Airlie (1):</p> +<ul> + <li>glsl: fix subroutine lowering reusing actual parmaters</li> +</ul> + +<p>Emil Velikov (6):</p> +<ul> + <li>docs: add sha256 checksums for 11.1.1</li> + <li>cherry-ignore: drop the i965/kbl .num_slices patch</li> + <li>i915: correctly parse/set the context flags</li> + <li>targets/dri: android: use WHOLE static libraries</li> + <li>egl/dri2: expose srgb configs when KHR_gl_colorspace is available</li> + <li>Update version to 11.1.2</li> +</ul> + +<p>Eric Anholt (2):</p> +<ul> + <li>vc4: Don't record the seqno of a failed job submit.</li> + <li>vc4: Throttle outstanding rendering after submission.</li> +</ul> + +<p>François Tigeot (1):</p> +<ul> + <li>gallium: Add DragonFly support</li> +</ul> + +<p>Grazvydas Ignotas (1):</p> +<ul> + <li>r600g: don't leak driver const buffers</li> +</ul> + +<p>Ian Romanick (2):</p> +<ul> + <li>meta/blit: Restore GL_DEPTH_STENCIL_TEXTURE_MODE state for GL_TEXTURE_RECTANGLE</li> + <li>meta: Use internal functions to set texture parameters</li> +</ul> + +<p>Ilia Mirkin (6):</p> +<ul> + <li>st/mesa: use surface format to generate mipmaps when available</li> + <li>glsl: always compute proper varying type, irrespective of varying packing</li> + <li>nvc0: avoid crashing when there are holes in vertex array bindings</li> + <li>nv50,nvc0: fix buffer clearing to respect engine alignment requirements</li> + <li>nv50/ir: fix false global CSE on instructions with multiple defs</li> + <li>st/mesa: treat a write as a read for range purposes</li> +</ul> + +<p>Jason Ekstrand (3):</p> +<ul> + <li>i965/vec4: Use UW type for multiply into accumulator on GEN8+</li> + <li>i965/fs/generator: Take an actual shader stage rather than a string</li> + <li>i965/fs: Always set channel 2 of texture headers in some stages</li> +</ul> + +<p>Jose Fonseca (2):</p> +<ul> + <li>scons: Conditionally use DRM module on pipe-loader.</li> + <li>pipe-loader: Fix PATH_MAX define on MSVC.</li> +</ul> + +<p>Karol Herbst (1):</p> +<ul> + <li>nv50/ir: fix memory corruption when spilling and redoing RA</li> +</ul> + +<p>Kenneth Graunke (2):</p> +<ul> + <li>glsl: Make bitfield_insert/extract and bfi/bfm non-vectorizable.</li> + <li>glsl: Allow implicit int -> uint conversions for bitwise operators (&, ^, |).</li> +</ul> + +<p>Leo Liu (2):</p> +<ul> + <li>vl: add zig zag scan for list 4x4</li> + <li>st/omx/dec/h264: fix corruption when scaling matrix present flag set</li> +</ul> + +<p>Marek Olšák (1):</p> +<ul> + <li>radeonsi: don't miss changes to SPI_TMPRING_SIZE</li> +</ul> + +<p>Nicolai Hähnle (11):</p> +<ul> + <li>mesa/bufferobj: make _mesa_delete_buffer_object externally accessible</li> + <li>st/mesa: use _mesa_delete_buffer_object</li> + <li>radeon: use _mesa_delete_buffer_object</li> + <li>i915: use _mesa_delete_buffer_object</li> + <li>i965: use _mesa_delete_buffer_object</li> + <li>util/u_pstipple.c: copy immediates during transformation</li> + <li>radeonsi: extract the VGT_GS_MODE calculation into its own function</li> + <li>radeonsi: ensure that VGT_GS_MODE is sent when necessary</li> + <li>radeonsi: add DCC buffer for sampler views on new CS</li> + <li>st/mesa: use the correct address generation functions in st_TexSubImage blit</li> + <li>radeonsi: fix discard-only fragment shaders (11.1 version)</li> +</ul> + +<p>Timothy Arceri (4):</p> +<ul> + <li>glsl: fix segfault linking subroutine uniform with explicit location</li> + <li>mesa: fix segfault in glUniformSubroutinesuiv()</li> + <li>glsl: fix interface block error message</li> + <li>glsl: create helper to remove outer vertex index array used by some stages</li> +</ul> + + +</div> +</body> +</html> diff --git a/include/c99/inttypes.h b/include/c99/inttypes.h deleted file mode 100644 index 4b3828a2162..00000000000 --- a/include/c99/inttypes.h +++ /dev/null @@ -1,305 +0,0 @@ -// ISO C9x compliant inttypes.h for Microsoft Visual Studio -// Based on ISO/IEC 9899:TC2 Committee draft (May 6, 2005) WG14/N1124 -// -// Copyright (c) 2006 Alexander Chemeris -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. The name of the author may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO -// EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _MSC_VER // [ -#error "Use this header only with Microsoft Visual C++ compilers!" -#endif // _MSC_VER ] - -#ifndef _MSC_INTTYPES_H_ // [ -#define _MSC_INTTYPES_H_ - -#if _MSC_VER > 1000 -#pragma once -#endif - -#include "stdint.h" - -// 7.8 Format conversion of integer types - -typedef struct { - intmax_t quot; - intmax_t rem; -} imaxdiv_t; - -// 7.8.1 Macros for format specifiers - -#if !defined(__cplusplus) || defined(__STDC_FORMAT_MACROS) // [ See footnote 185 at page 198 - -// The fprintf macros for signed integers are: -#define PRId8 "d" -#define PRIi8 "i" -#define PRIdLEAST8 "d" -#define PRIiLEAST8 "i" -#define PRIdFAST8 "d" -#define PRIiFAST8 "i" - -#define PRId16 "hd" -#define PRIi16 "hi" -#define PRIdLEAST16 "hd" -#define PRIiLEAST16 "hi" -#define PRIdFAST16 "hd" -#define PRIiFAST16 "hi" - -#define PRId32 "I32d" -#define PRIi32 "I32i" -#define PRIdLEAST32 "I32d" -#define PRIiLEAST32 "I32i" -#define PRIdFAST32 "I32d" -#define PRIiFAST32 "I32i" - -#define PRId64 "I64d" -#define PRIi64 "I64i" -#define PRIdLEAST64 "I64d" -#define PRIiLEAST64 "I64i" -#define PRIdFAST64 "I64d" -#define PRIiFAST64 "I64i" - -#define PRIdMAX "I64d" -#define PRIiMAX "I64i" - -#define PRIdPTR "Id" -#define PRIiPTR "Ii" - -// The fprintf macros for unsigned integers are: -#define PRIo8 "o" -#define PRIu8 "u" -#define PRIx8 "x" -#define PRIX8 "X" -#define PRIoLEAST8 "o" -#define PRIuLEAST8 "u" -#define PRIxLEAST8 "x" -#define PRIXLEAST8 "X" -#define PRIoFAST8 "o" -#define PRIuFAST8 "u" -#define PRIxFAST8 "x" -#define PRIXFAST8 "X" - -#define PRIo16 "ho" -#define PRIu16 "hu" -#define PRIx16 "hx" -#define PRIX16 "hX" -#define PRIoLEAST16 "ho" -#define PRIuLEAST16 "hu" -#define PRIxLEAST16 "hx" -#define PRIXLEAST16 "hX" -#define PRIoFAST16 "ho" -#define PRIuFAST16 "hu" -#define PRIxFAST16 "hx" -#define PRIXFAST16 "hX" - -#define PRIo32 "I32o" -#define PRIu32 "I32u" -#define PRIx32 "I32x" -#define PRIX32 "I32X" -#define PRIoLEAST32 "I32o" -#define PRIuLEAST32 "I32u" -#define PRIxLEAST32 "I32x" -#define PRIXLEAST32 "I32X" -#define PRIoFAST32 "I32o" -#define PRIuFAST32 "I32u" -#define PRIxFAST32 "I32x" -#define PRIXFAST32 "I32X" - -#define PRIo64 "I64o" -#define PRIu64 "I64u" -#define PRIx64 "I64x" -#define PRIX64 "I64X" -#define PRIoLEAST64 "I64o" -#define PRIuLEAST64 "I64u" -#define PRIxLEAST64 "I64x" -#define PRIXLEAST64 "I64X" -#define PRIoFAST64 "I64o" -#define PRIuFAST64 "I64u" -#define PRIxFAST64 "I64x" -#define PRIXFAST64 "I64X" - -#define PRIoMAX "I64o" -#define PRIuMAX "I64u" -#define PRIxMAX "I64x" -#define PRIXMAX "I64X" - -#define PRIoPTR "Io" -#define PRIuPTR "Iu" -#define PRIxPTR "Ix" -#define PRIXPTR "IX" - -// The fscanf macros for signed integers are: -#define SCNd8 "d" -#define SCNi8 "i" -#define SCNdLEAST8 "d" -#define SCNiLEAST8 "i" -#define SCNdFAST8 "d" -#define SCNiFAST8 "i" - -#define SCNd16 "hd" -#define SCNi16 "hi" -#define SCNdLEAST16 "hd" -#define SCNiLEAST16 "hi" -#define SCNdFAST16 "hd" -#define SCNiFAST16 "hi" - -#define SCNd32 "ld" -#define SCNi32 "li" -#define SCNdLEAST32 "ld" -#define SCNiLEAST32 "li" -#define SCNdFAST32 "ld" -#define SCNiFAST32 "li" - -#define SCNd64 "I64d" -#define SCNi64 "I64i" -#define SCNdLEAST64 "I64d" -#define SCNiLEAST64 "I64i" -#define SCNdFAST64 "I64d" -#define SCNiFAST64 "I64i" - -#define SCNdMAX "I64d" -#define SCNiMAX "I64i" - -#ifdef _WIN64 // [ -# define SCNdPTR "I64d" -# define SCNiPTR "I64i" -#else // _WIN64 ][ -# define SCNdPTR "ld" -# define SCNiPTR "li" -#endif // _WIN64 ] - -// The fscanf macros for unsigned integers are: -#define SCNo8 "o" -#define SCNu8 "u" -#define SCNx8 "x" -#define SCNX8 "X" -#define SCNoLEAST8 "o" -#define SCNuLEAST8 "u" -#define SCNxLEAST8 "x" -#define SCNXLEAST8 "X" -#define SCNoFAST8 "o" -#define SCNuFAST8 "u" -#define SCNxFAST8 "x" -#define SCNXFAST8 "X" - -#define SCNo16 "ho" -#define SCNu16 "hu" -#define SCNx16 "hx" -#define SCNX16 "hX" -#define SCNoLEAST16 "ho" -#define SCNuLEAST16 "hu" -#define SCNxLEAST16 "hx" -#define SCNXLEAST16 "hX" -#define SCNoFAST16 "ho" -#define SCNuFAST16 "hu" -#define SCNxFAST16 "hx" -#define SCNXFAST16 "hX" - -#define SCNo32 "lo" -#define SCNu32 "lu" -#define SCNx32 "lx" -#define SCNX32 "lX" -#define SCNoLEAST32 "lo" -#define SCNuLEAST32 "lu" -#define SCNxLEAST32 "lx" -#define SCNXLEAST32 "lX" -#define SCNoFAST32 "lo" -#define SCNuFAST32 "lu" -#define SCNxFAST32 "lx" -#define SCNXFAST32 "lX" - -#define SCNo64 "I64o" -#define SCNu64 "I64u" -#define SCNx64 "I64x" -#define SCNX64 "I64X" -#define SCNoLEAST64 "I64o" -#define SCNuLEAST64 "I64u" -#define SCNxLEAST64 "I64x" -#define SCNXLEAST64 "I64X" -#define SCNoFAST64 "I64o" -#define SCNuFAST64 "I64u" -#define SCNxFAST64 "I64x" -#define SCNXFAST64 "I64X" - -#define SCNoMAX "I64o" -#define SCNuMAX "I64u" -#define SCNxMAX "I64x" -#define SCNXMAX "I64X" - -#ifdef _WIN64 // [ -# define SCNoPTR "I64o" -# define SCNuPTR "I64u" -# define SCNxPTR "I64x" -# define SCNXPTR "I64X" -#else // _WIN64 ][ -# define SCNoPTR "lo" -# define SCNuPTR "lu" -# define SCNxPTR "lx" -# define SCNXPTR "lX" -#endif // _WIN64 ] - -#endif // __STDC_FORMAT_MACROS ] - -// 7.8.2 Functions for greatest-width integer types - -// 7.8.2.1 The imaxabs function -#define imaxabs _abs64 - -// 7.8.2.2 The imaxdiv function - -// This is modified version of div() function from Microsoft's div.c found -// in %MSVC.NET%\crt\src\div.c -#ifdef STATIC_IMAXDIV // [ -static -#else // STATIC_IMAXDIV ][ -_inline -#endif // STATIC_IMAXDIV ] -imaxdiv_t __cdecl imaxdiv(intmax_t numer, intmax_t denom) -{ - imaxdiv_t result; - - result.quot = numer / denom; - result.rem = numer % denom; - - if (numer < 0 && result.rem > 0) { - // did division wrong; must fix up - ++result.quot; - result.rem -= denom; - } - - return result; -} - -// 7.8.2.3 The strtoimax and strtoumax functions -#define strtoimax _strtoi64 -#define strtoumax _strtoui64 - -// 7.8.2.4 The wcstoimax and wcstoumax functions -#define wcstoimax _wcstoi64 -#define wcstoumax _wcstoui64 - - -#endif // _MSC_INTTYPES_H_ ] diff --git a/include/c99/stdbool.h b/include/c99/stdbool.h deleted file mode 100644 index 856be5fb0f6..00000000000 --- a/include/c99/stdbool.h +++ /dev/null @@ -1,46 +0,0 @@ -/************************************************************************** - * - * Copyright 2007-2010 VMware, Inc. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - **************************************************************************/ - -#ifndef _STDBOOL_H_ -#define _STDBOOL_H_ - -#ifndef __cplusplus - -#define false 0 -#define true 1 -#define bool _Bool - -/* For compilers that don't have the builtin _Bool type. */ -#if (defined(_MSC_VER) && _MSC_VER < 1800) -typedef unsigned char _Bool; -#endif - -#endif /* !__cplusplus */ - -#define __bool_true_false_are_defined 1 - -#endif /* !_STDBOOL_H_ */ diff --git a/include/c99/stdint.h b/include/c99/stdint.h deleted file mode 100644 index d02608a5972..00000000000 --- a/include/c99/stdint.h +++ /dev/null @@ -1,247 +0,0 @@ -// ISO C9x compliant stdint.h for Microsoft Visual Studio -// Based on ISO/IEC 9899:TC2 Committee draft (May 6, 2005) WG14/N1124 -// -// Copyright (c) 2006-2008 Alexander Chemeris -// -// Redistribution and use in source and binary forms, with or without -// modification, are permitted provided that the following conditions are met: -// -// 1. Redistributions of source code must retain the above copyright notice, -// this list of conditions and the following disclaimer. -// -// 2. Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in the -// documentation and/or other materials provided with the distribution. -// -// 3. The name of the author may be used to endorse or promote products -// derived from this software without specific prior written permission. -// -// THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED -// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO -// EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -// OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// -/////////////////////////////////////////////////////////////////////////////// - -#ifndef _MSC_VER // [ -#error "Use this header only with Microsoft Visual C++ compilers!" -#endif // _MSC_VER ] - -#ifndef _MSC_STDINT_H_ // [ -#define _MSC_STDINT_H_ - -#if _MSC_VER > 1000 -#pragma once -#endif - -#include <limits.h> - -// For Visual Studio 6 in C++ mode and for many Visual Studio versions when -// compiling for ARM we should wrap <wchar.h> include with 'extern "C++" {}' -// or compiler give many errors like this: -// error C2733: second C linkage of overloaded function 'wmemchr' not allowed -#ifdef __cplusplus -extern "C" { -#endif -# include <wchar.h> -#ifdef __cplusplus -} -#endif - -// Define _W64 macros to mark types changing their size, like intptr_t. -#ifndef _W64 -# if !defined(__midl) && (defined(_X86_) || defined(_M_IX86)) && _MSC_VER >= 1300 -# define _W64 __w64 -# else -# define _W64 -# endif -#endif - - -// 7.18.1 Integer types - -// 7.18.1.1 Exact-width integer types - -// Visual Studio 6 and Embedded Visual C++ 4 doesn't -// realize that, e.g. char has the same size as __int8 -// so we give up on __intX for them. -#if (_MSC_VER < 1300) - typedef signed char int8_t; - typedef signed short int16_t; - typedef signed int int32_t; - typedef unsigned char uint8_t; - typedef unsigned short uint16_t; - typedef unsigned int uint32_t; -#else - typedef signed __int8 int8_t; - typedef signed __int16 int16_t; - typedef signed __int32 int32_t; - typedef unsigned __int8 uint8_t; - typedef unsigned __int16 uint16_t; - typedef unsigned __int32 uint32_t; -#endif -typedef signed __int64 int64_t; -typedef unsigned __int64 uint64_t; - - -// 7.18.1.2 Minimum-width integer types -typedef int8_t int_least8_t; -typedef int16_t int_least16_t; -typedef int32_t int_least32_t; -typedef int64_t int_least64_t; -typedef uint8_t uint_least8_t; -typedef uint16_t uint_least16_t; -typedef uint32_t uint_least32_t; -typedef uint64_t uint_least64_t; - -// 7.18.1.3 Fastest minimum-width integer types -typedef int8_t int_fast8_t; -typedef int16_t int_fast16_t; -typedef int32_t int_fast32_t; -typedef int64_t int_fast64_t; -typedef uint8_t uint_fast8_t; -typedef uint16_t uint_fast16_t; -typedef uint32_t uint_fast32_t; -typedef uint64_t uint_fast64_t; - -// 7.18.1.4 Integer types capable of holding object pointers -#ifdef _WIN64 // [ - typedef signed __int64 intptr_t; - typedef unsigned __int64 uintptr_t; -#else // _WIN64 ][ - typedef _W64 signed int intptr_t; - typedef _W64 unsigned int uintptr_t; -#endif // _WIN64 ] - -// 7.18.1.5 Greatest-width integer types -typedef int64_t intmax_t; -typedef uint64_t uintmax_t; - - -// 7.18.2 Limits of specified-width integer types - -#if !defined(__cplusplus) || defined(__STDC_LIMIT_MACROS) // [ See footnote 220 at page 257 and footnote 221 at page 259 - -// 7.18.2.1 Limits of exact-width integer types -#define INT8_MIN ((int8_t)_I8_MIN) -#define INT8_MAX _I8_MAX -#define INT16_MIN ((int16_t)_I16_MIN) -#define INT16_MAX _I16_MAX -#define INT32_MIN ((int32_t)_I32_MIN) -#define INT32_MAX _I32_MAX -#define INT64_MIN ((int64_t)_I64_MIN) -#define INT64_MAX _I64_MAX -#define UINT8_MAX _UI8_MAX -#define UINT16_MAX _UI16_MAX -#define UINT32_MAX _UI32_MAX -#define UINT64_MAX _UI64_MAX - -// 7.18.2.2 Limits of minimum-width integer types -#define INT_LEAST8_MIN INT8_MIN -#define INT_LEAST8_MAX INT8_MAX -#define INT_LEAST16_MIN INT16_MIN -#define INT_LEAST16_MAX INT16_MAX -#define INT_LEAST32_MIN INT32_MIN -#define INT_LEAST32_MAX INT32_MAX -#define INT_LEAST64_MIN INT64_MIN -#define INT_LEAST64_MAX INT64_MAX -#define UINT_LEAST8_MAX UINT8_MAX -#define UINT_LEAST16_MAX UINT16_MAX -#define UINT_LEAST32_MAX UINT32_MAX -#define UINT_LEAST64_MAX UINT64_MAX - -// 7.18.2.3 Limits of fastest minimum-width integer types -#define INT_FAST8_MIN INT8_MIN -#define INT_FAST8_MAX INT8_MAX -#define INT_FAST16_MIN INT16_MIN -#define INT_FAST16_MAX INT16_MAX -#define INT_FAST32_MIN INT32_MIN -#define INT_FAST32_MAX INT32_MAX -#define INT_FAST64_MIN INT64_MIN -#define INT_FAST64_MAX INT64_MAX -#define UINT_FAST8_MAX UINT8_MAX -#define UINT_FAST16_MAX UINT16_MAX -#define UINT_FAST32_MAX UINT32_MAX -#define UINT_FAST64_MAX UINT64_MAX - -// 7.18.2.4 Limits of integer types capable of holding object pointers -#ifdef _WIN64 // [ -# define INTPTR_MIN INT64_MIN -# define INTPTR_MAX INT64_MAX -# define UINTPTR_MAX UINT64_MAX -#else // _WIN64 ][ -# define INTPTR_MIN INT32_MIN -# define INTPTR_MAX INT32_MAX -# define UINTPTR_MAX UINT32_MAX -#endif // _WIN64 ] - -// 7.18.2.5 Limits of greatest-width integer types -#define INTMAX_MIN INT64_MIN -#define INTMAX_MAX INT64_MAX -#define UINTMAX_MAX UINT64_MAX - -// 7.18.3 Limits of other integer types - -#ifdef _WIN64 // [ -# define PTRDIFF_MIN _I64_MIN -# define PTRDIFF_MAX _I64_MAX -#else // _WIN64 ][ -# define PTRDIFF_MIN _I32_MIN -# define PTRDIFF_MAX _I32_MAX -#endif // _WIN64 ] - -#define SIG_ATOMIC_MIN INT_MIN -#define SIG_ATOMIC_MAX INT_MAX - -#ifndef SIZE_MAX // [ -# ifdef _WIN64 // [ -# define SIZE_MAX _UI64_MAX -# else // _WIN64 ][ -# define SIZE_MAX _UI32_MAX -# endif // _WIN64 ] -#endif // SIZE_MAX ] - -// WCHAR_MIN and WCHAR_MAX are also defined in <wchar.h> -#ifndef WCHAR_MIN // [ -# define WCHAR_MIN 0 -#endif // WCHAR_MIN ] -#ifndef WCHAR_MAX // [ -# define WCHAR_MAX _UI16_MAX -#endif // WCHAR_MAX ] - -#define WINT_MIN 0 -#define WINT_MAX _UI16_MAX - -#endif // __STDC_LIMIT_MACROS ] - - -// 7.18.4 Limits of other integer types - -#if !defined(__cplusplus) || defined(__STDC_CONSTANT_MACROS) // [ See footnote 224 at page 260 - -// 7.18.4.1 Macros for minimum-width integer constants - -#define INT8_C(val) val##i8 -#define INT16_C(val) val##i16 -#define INT32_C(val) val##i32 -#define INT64_C(val) val##i64 - -#define UINT8_C(val) val##ui8 -#define UINT16_C(val) val##ui16 -#define UINT32_C(val) val##ui32 -#define UINT64_C(val) val##ui64 - -// 7.18.4.2 Macros for greatest-width integer constants -#define INTMAX_C INT64_C -#define UINTMAX_C UINT64_C - -#endif // __STDC_CONSTANT_MACROS ] - - -#endif // _MSC_STDINT_H_ ] diff --git a/include/c99_compat.h b/include/c99_compat.h index 4be5b7e1259..b55ad9c181d 100644 --- a/include/c99_compat.h +++ b/include/c99_compat.h @@ -36,17 +36,17 @@ */ #if defined(_MSC_VER) -# if _MSC_VER < 1500 -# error "Microsoft Visual Studio 2008 or higher required" +# if _MSC_VER < 1800 +# error "Microsoft Visual Studio 2013 or higher required" # endif /* - * Visual Studio 2012 will complain if we define the `inline` keyword, but + * Visual Studio will complain if we define the `inline` keyword, but * actually it only supports the keyword on C++. * * To avoid this the _ALLOW_KEYWORD_MACROS must be set. */ -# if (_MSC_VER >= 1700) && !defined(_ALLOW_KEYWORD_MACROS) +# if !defined(_ALLOW_KEYWORD_MACROS) # define _ALLOW_KEYWORD_MACROS # endif diff --git a/include/c99_math.h b/include/c99_math.h index 8a67fb133d6..250e08d44cf 100644 --- a/include/c99_math.h +++ b/include/c99_math.h @@ -38,55 +38,16 @@ #include "c99_compat.h" -#if defined(_MSC_VER) - /* This is to ensure that we get M_PI, etc. definitions */ -#if !defined(_USE_MATH_DEFINES) +#if defined(_MSC_VER) && !defined(_USE_MATH_DEFINES) #error _USE_MATH_DEFINES define required when building with MSVC #endif -#if _MSC_VER < 1800 -#define isfinite(x) _finite((double)(x)) -#define isnan(x) _isnan((double)(x)) -#endif /* _MSC_VER < 1800 */ - -#if _MSC_VER < 1800 -static inline double log2( double x ) -{ - const double invln2 = 1.442695041; - return log( x ) * invln2; -} - -static inline double -round(double x) -{ - return x >= 0.0 ? floor(x + 0.5) : ceil(x - 0.5); -} - -static inline float -roundf(float x) -{ - return x >= 0.0f ? floorf(x + 0.5f) : ceilf(x - 0.5f); -} -#endif - -#ifndef INFINITY -#include <float.h> // DBL_MAX -#define INFINITY (DBL_MAX + DBL_MAX) -#endif - -#ifndef NAN -#define NAN (INFINITY - INFINITY) -#endif - -#endif /* _MSC_VER */ - -#if (defined(_MSC_VER) && _MSC_VER < 1800) || \ - (!defined(_MSC_VER) && \ - __STDC_VERSION__ < 199901L && \ - (!defined(_XOPEN_SOURCE) || _XOPEN_SOURCE < 600) && \ - !defined(__cplusplus)) +#if !defined(_MSC_VER) && \ + __STDC_VERSION__ < 199901L && \ + (!defined(_XOPEN_SOURCE) || _XOPEN_SOURCE < 600) && \ + !defined(__cplusplus) static inline long int lrint(double d) diff --git a/scons/gallium.py b/scons/gallium.py index 6dcd95233c3..46520168a02 100755 --- a/scons/gallium.py +++ b/scons/gallium.py @@ -94,16 +94,8 @@ def msvc2013_compat(env): '-Werror=pointer-arith', ]) -def msvc2008_compat(env): - msvc2013_compat(env) - if env['gcc']: - env.Append(CFLAGS = [ - '-Werror=declaration-after-statement', - ]) - def createMSVCCompatMethods(env): env.AddMethod(msvc2013_compat, 'MSVC2013Compat') - env.AddMethod(msvc2008_compat, 'MSVC2008Compat') def num_jobs(): @@ -479,20 +471,12 @@ def generate(env): # See also: # - http://msdn.microsoft.com/en-us/library/19z1t1wy.aspx # - cl /? - if 'MSVC_VERSION' not in env or distutils.version.LooseVersion(env['MSVC_VERSION']) < distutils.version.LooseVersion('12.0'): - # Use bundled stdbool.h and stdint.h headers for older MSVC - # versions. stdint.h was introduced in MSVC 2010, but stdbool.h - # was only introduced in MSVC 2013. - top_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), '..')) - env.Append(CPPPATH = [os.path.join(top_dir, 'include/c99')]) if env['build'] == 'debug': ccflags += [ '/Od', # disable optimizations '/Oi', # enable intrinsic functions ] else: - if 'MSVC_VERSION' in env and distutils.version.LooseVersion(env['MSVC_VERSION']) < distutils.version.LooseVersion('11.0'): - print 'scons: warning: Visual Studio versions prior to 2012 are known to produce incorrect code when optimizations are enabled ( https://bugs.freedesktop.org/show_bug.cgi?id=58718 )' ccflags += [ '/O2', # optimize for speed ] diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp index a4842400288..9e811661a2e 100644 --- a/src/compiler/glsl/ast_to_hir.cpp +++ b/src/compiler/glsl/ast_to_hir.cpp @@ -6268,13 +6268,24 @@ ast_process_struct_or_iface_block_members(exec_list *instructions, decl_list->type->specifier->hir(instructions, state); - /* Section 10.9 of the GLSL ES 1.00 specification states that - * embedded structure definitions have been removed from the language. + /* Section 4.1.8 (Structures) of the GLSL 1.10 spec says: + * + * "Anonymous structures are not supported; so embedded structures + * must have a declarator. A name given to an embedded struct is + * scoped at the same level as the struct it is embedded in." + * + * The same section of the GLSL 1.20 spec says: + * + * "Anonymous structures are not supported. Embedded structures are + * not supported." + * + * The GLSL ES 1.00 and 3.00 specs have similar langauge. So, we allow + * embedded structures in 1.10 only. */ - if (state->es_shader && decl_list->type->specifier->structure != NULL) { - _mesa_glsl_error(&loc, state, "embedded structure definitions are " - "not allowed in GLSL ES 1.00"); - } + if (state->language_version != 110 && + decl_list->type->specifier->structure != NULL) + _mesa_glsl_error(&loc, state, + "embedded structure declarations are not allowed"); const glsl_type *decl_type = decl_list->type->glsl_type(& type_name, state); @@ -6293,30 +6304,28 @@ ast_process_struct_or_iface_block_members(exec_list *instructions, */ assert(decl_type); - if (is_interface && decl_type->contains_opaque()) { - _mesa_glsl_error(&loc, state, - "uniform/buffer in non-default interface block contains " - "opaque variable"); - } - - if (decl_type->contains_atomic()) { - /* From section 4.1.7.3 of the GLSL 4.40 spec: - * - * "Members of structures cannot be declared as atomic counter - * types." - */ - _mesa_glsl_error(&loc, state, "atomic counter in structure, " - "shader storage block or uniform block"); - } + if (is_interface) { + if (decl_type->contains_opaque()) { + _mesa_glsl_error(&loc, state, "uniform/buffer in non-default " + "interface block contains opaque variable"); + } + } else { + if (decl_type->contains_atomic()) { + /* From section 4.1.7.3 of the GLSL 4.40 spec: + * + * "Members of structures cannot be declared as atomic counter + * types." + */ + _mesa_glsl_error(&loc, state, "atomic counter in structure"); + } - if (decl_type->contains_image()) { - /* FINISHME: Same problem as with atomic counters. - * FINISHME: Request clarification from Khronos and add - * FINISHME: spec quotation here. - */ - _mesa_glsl_error(&loc, state, - "image in structure, shader storage block or " - "uniform block"); + if (decl_type->contains_image()) { + /* FINISHME: Same problem as with atomic counters. + * FINISHME: Request clarification from Khronos and add + * FINISHME: spec quotation here. + */ + _mesa_glsl_error(&loc, state, "image in structure"); + } } if (qual->flags.q.explicit_binding) { @@ -6515,33 +6524,6 @@ ast_struct_specifier::hir(exec_list *instructions, { YYLTYPE loc = this->get_location(); - /* Section 4.1.8 (Structures) of the GLSL 1.10 spec says: - * - * "Anonymous structures are not supported; so embedded structures must - * have a declarator. A name given to an embedded struct is scoped at - * the same level as the struct it is embedded in." - * - * The same section of the GLSL 1.20 spec says: - * - * "Anonymous structures are not supported. Embedded structures are not - * supported. - * - * struct S { float f; }; - * struct T { - * S; // Error: anonymous structures disallowed - * struct { ... }; // Error: embedded structures disallowed - * S s; // Okay: nested structures with name are allowed - * };" - * - * The GLSL ES 1.00 and 3.00 specs have similar langauge and examples. So, - * we allow embedded structures in 1.10 only. - */ - if (state->language_version != 110 && state->struct_specifier_depth != 0) - _mesa_glsl_error(&loc, state, - "embedded structure declarations are not allowed"); - - state->struct_specifier_depth++; - unsigned expl_location = 0; if (layout && layout->flags.q.explicit_location) { if (!process_qualifier_constant(state, &loc, "location", @@ -6584,8 +6566,6 @@ ast_struct_specifier::hir(exec_list *instructions, } } - state->struct_specifier_depth--; - /* Structure type definitions do not have r-values. */ return NULL; @@ -6705,11 +6685,6 @@ ast_interface_block::hir(exec_list *instructions, exec_list declared_variables; glsl_struct_field *fields; - /* Treat an interface block as one level of nesting, so that embedded struct - * specifiers will be disallowed. - */ - state->struct_specifier_depth++; - /* For blocks that accept memory qualifiers (i.e. shader storage), verify * that we don't have incompatible qualifiers */ @@ -6752,8 +6727,6 @@ ast_interface_block::hir(exec_list *instructions, qual_stream, expl_location); - state->struct_specifier_depth--; - if (!redeclaring_per_vertex) { validate_identifier(this->block_name, loc, state); diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp index 73d378c4bc9..86cf091b4fe 100644 --- a/src/compiler/glsl/glsl_parser_extras.cpp +++ b/src/compiler/glsl/glsl_parser_extras.cpp @@ -69,8 +69,6 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct gl_context *_ctx, this->error = false; this->loop_nesting_ast = NULL; - this->struct_specifier_depth = 0; - this->uses_builtin_functions = false; /* Set default language version and extensions */ diff --git a/src/compiler/glsl/glsl_parser_extras.h b/src/compiler/glsl/glsl_parser_extras.h index a905b564787..4dacc2ac62b 100644 --- a/src/compiler/glsl/glsl_parser_extras.h +++ b/src/compiler/glsl/glsl_parser_extras.h @@ -290,13 +290,6 @@ struct _mesa_glsl_parse_state { gl_shader_stage stage; /** - * Number of nested struct_specifier levels - * - * Outside a struct_specifier, this is zero. - */ - unsigned struct_specifier_depth; - - /** * Default uniform layout qualifiers tracked during parsing. * Currently affects uniform blocks and uniform buffer variables in * those blocks. diff --git a/src/compiler/glsl/program.h b/src/compiler/glsl/program.h index 64f54635f62..31bb9aa2435 100644 --- a/src/compiler/glsl/program.h +++ b/src/compiler/glsl/program.h @@ -22,12 +22,15 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "main/core.h" #ifdef __cplusplus extern "C" { #endif +struct gl_context; +struct gl_shader; +struct gl_shader_program; + extern void _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader, bool dump_ast, bool dump_hir); diff --git a/src/gallium/auxiliary/Makefile.am b/src/gallium/auxiliary/Makefile.am index 0ac5c9802f2..82c2869b99b 100644 --- a/src/gallium/auxiliary/Makefile.am +++ b/src/gallium/auxiliary/Makefile.am @@ -8,11 +8,11 @@ AM_CFLAGS = \ -I$(top_srcdir)/src/gallium/auxiliary/util \ $(GALLIUM_CFLAGS) \ $(VISIBILITY_CFLAGS) \ - $(MSVC2008_COMPAT_CFLAGS) + $(MSVC2013_COMPAT_CFLAGS) AM_CXXFLAGS = \ $(VISIBILITY_CXXFLAGS) \ - $(MSVC2008_COMPAT_CXXFLAGS) + $(MSVC2013_COMPAT_CXXFLAGS) libgallium_nir_la_SOURCES = \ $(NIR_SOURCES) diff --git a/src/gallium/auxiliary/SConscript b/src/gallium/auxiliary/SConscript index d5fa880c7f2..3d83d4467b4 100644 --- a/src/gallium/auxiliary/SConscript +++ b/src/gallium/auxiliary/SConscript @@ -10,7 +10,7 @@ env.Append(CPPPATH = [ env = env.Clone() -env.MSVC2008Compat() +env.MSVC2013Compat() env.CodeGenerate( target = 'indices/u_indices_gen.c', diff --git a/src/gallium/auxiliary/pipe-loader/SConscript b/src/gallium/auxiliary/pipe-loader/SConscript index c611fb892f8..14e1b350aea 100644 --- a/src/gallium/auxiliary/pipe-loader/SConscript +++ b/src/gallium/auxiliary/pipe-loader/SConscript @@ -2,7 +2,7 @@ Import('*') env = env.Clone() -env.MSVC2008Compat() +env.MSVC2013Compat() env.Append(CPPPATH = [ '#/src/loader', diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c b/src/gallium/auxiliary/util/u_cpu_detect.c index a84de4fef7b..10b090216d7 100644 --- a/src/gallium/auxiliary/util/u_cpu_detect.c +++ b/src/gallium/auxiliary/util/u_cpu_detect.c @@ -283,8 +283,7 @@ PIPE_ALIGN_STACK static inline boolean sse2_has_daz(void) fxarea.mxcsr_mask = 0; #if defined(PIPE_CC_GCC) __asm __volatile ("fxsave %0" : "+m" (fxarea)); -#elif (defined(PIPE_CC_MSVC) && _MSC_VER >= 1700) || defined(PIPE_CC_ICL) - /* 1700 = Visual Studio 2012 */ +#elif defined(PIPE_CC_MSVC) || defined(PIPE_CC_ICL) _fxsave(&fxarea); #else fxarea.mxcsr_mask = 0; diff --git a/src/gallium/drivers/llvmpipe/Makefile.am b/src/gallium/drivers/llvmpipe/Makefile.am index 1d3853e41a6..85ae0ae13d8 100644 --- a/src/gallium/drivers/llvmpipe/Makefile.am +++ b/src/gallium/drivers/llvmpipe/Makefile.am @@ -26,11 +26,11 @@ include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ $(GALLIUM_DRIVER_CFLAGS) \ $(LLVM_CFLAGS) \ - $(MSVC2008_COMPAT_CFLAGS) + $(MSVC2013_COMPAT_CFLAGS) AM_CXXFLAGS= \ $(GALLIUM_DRIVER_CXXFLAGS) \ $(LLVM_CXXFLAGS) \ - $(MSVC2008_COMPAT_CXXFLAGS) + $(MSVC2013_COMPAT_CXXFLAGS) noinst_LTLIBRARIES = libllvmpipe.la diff --git a/src/gallium/drivers/llvmpipe/SConscript b/src/gallium/drivers/llvmpipe/SConscript index 3a51efcd506..11cc3bcc858 100644 --- a/src/gallium/drivers/llvmpipe/SConscript +++ b/src/gallium/drivers/llvmpipe/SConscript @@ -9,7 +9,7 @@ if not env['llvm']: env = env.Clone() -env.MSVC2008Compat() +env.MSVC2013Compat() llvmpipe = env.ConvenienceLibrary( target = 'llvmpipe', diff --git a/src/gallium/drivers/nouveau/nv50/nv50_context.h b/src/gallium/drivers/nouveau/nv50/nv50_context.h index 712d00ed2d3..342ec96d62c 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_context.h +++ b/src/gallium/drivers/nouveau/nv50/nv50_context.h @@ -230,9 +230,7 @@ void nv50_stream_output_validate(struct nv50_context *); extern void nv50_init_state_functions(struct nv50_context *); /* nv50_state_validate.c */ -/* @words: check for space before emitting relocs */ -extern bool nv50_state_validate(struct nv50_context *, uint32_t state_mask, - unsigned space_words); +bool nv50_state_validate(struct nv50_context *, uint32_t state_mask); /* nv50_surface.c */ extern void nv50_clear(struct pipe_context *, unsigned buffers, diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c index d14d603adc9..4af969997f2 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c @@ -510,7 +510,7 @@ static struct state_validate { }; bool -nv50_state_validate(struct nv50_context *nv50, uint32_t mask, unsigned words) +nv50_state_validate(struct nv50_context *nv50, uint32_t mask) { uint32_t state_mask; int ret; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c index ec5cf376227..c69fa5abb98 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c @@ -525,7 +525,7 @@ nv50_clear(struct pipe_context *pipe, unsigned buffers, uint32_t mode = 0; /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */ - if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2))) + if (!nv50_state_validate(nv50, NV50_NEW_FRAMEBUFFER)) return; /* We have to clear ALL of the layers, not up to the min number of layers @@ -1340,7 +1340,7 @@ nv50_blit_3d(struct nv50_context *nv50, const struct pipe_blit_info *info) nv50_blitctx_prepare_state(blit); - nv50_state_validate(nv50, ~0, 36); + nv50_state_validate(nv50, ~0); x_range = (float)info->src.box.width / (float)info->dst.box.width; y_range = (float)info->src.box.height / (float)info->dst.box.height; diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c index 60fa2bc06a8..5369d5207ee 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c @@ -790,7 +790,7 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) if (unlikely(nv50->num_so_targets && !nv50->gmtyprog)) nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode]; - nv50_state_validate(nv50, ~0, 8); /* 8 as minimum, we use flush_notify */ + nv50_state_validate(nv50, ~0); push->kick_notify = nv50_draw_vbo_kick_notify; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h index 4ab2ac41183..4a6ea867e85 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h @@ -258,8 +258,7 @@ extern void nvc0_init_state_functions(struct nvc0_context *); /* nvc0_state_validate.c */ void nvc0_validate_global_residents(struct nvc0_context *, struct nouveau_bufctx *, int bin); -extern bool nvc0_state_validate(struct nvc0_context *, uint32_t state_mask, - unsigned space_words); +bool nvc0_state_validate(struct nvc0_context *, uint32_t state_mask); /* nvc0_surface.c */ extern void nvc0_clear(struct pipe_context *, unsigned buffers, diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c index c17223a1b2b..e0d8ab01776 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c @@ -703,7 +703,7 @@ static struct state_validate { }; bool -nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask, unsigned words) +nvc0_state_validate(struct nvc0_context *nvc0, uint32_t mask) { uint32_t state_mask; int ret; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c index 71726d1aa59..e3843ca1bf1 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c @@ -693,7 +693,7 @@ nvc0_clear(struct pipe_context *pipe, unsigned buffers, uint32_t mode = 0; /* don't need NEW_BLEND, COLOR_MASK doesn't affect CLEAR_BUFFERS */ - if (!nvc0_state_validate(nvc0, NVC0_NEW_FRAMEBUFFER, 9 + (fb->nr_cbufs * 2))) + if (!nvc0_state_validate(nvc0, NVC0_NEW_FRAMEBUFFER)) return; if (buffers & PIPE_CLEAR_COLOR && fb->nr_cbufs) { @@ -1191,7 +1191,7 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct pipe_blit_info *info) nvc0_blitctx_prepare_state(blit); - nvc0_state_validate(nvc0, ~0, 48); + nvc0_state_validate(nvc0, ~0); x_range = (float)info->src.box.width / (float)info->dst.box.width; y_range = (float)info->src.box.height / (float)info->dst.box.height; diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c index 44aed1adeeb..032b3c125cf 100644 --- a/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c @@ -967,8 +967,7 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) IMMED_NVC0(push, NVC0_3D(PATCH_VERTICES), nvc0->state.patch_vertices); } - /* 8 as minimum to avoid immediate double validation of new buffers */ - nvc0_state_validate(nvc0, ~0, 8); + nvc0_state_validate(nvc0, ~0); if (nvc0->vertprog->vp.need_draw_parameters) { PUSH_SPACE(push, 9); diff --git a/src/gallium/drivers/r600/evergreen_compute.c b/src/gallium/drivers/r600/evergreen_compute.c index d92e691fdb8..56c7fb93f73 100644 --- a/src/gallium/drivers/r600/evergreen_compute.c +++ b/src/gallium/drivers/r600/evergreen_compute.c @@ -208,23 +208,6 @@ void *evergreen_create_compute_state( COMPUTE_DBG(ctx->screen, "*** evergreen_create_compute_state\n"); header = cso->prog; code = cso->prog + sizeof(struct pipe_llvm_program_header); -#if HAVE_LLVM < 0x0306 - (void)use_kill; - (void)p; - shader->llvm_ctx = LLVMContextCreate(); - shader->num_kernels = radeon_llvm_get_num_kernels(shader->llvm_ctx, - code, header->num_bytes); - shader->kernels = CALLOC(sizeof(struct r600_kernel), - shader->num_kernels); - { - unsigned i; - for (i = 0; i < shader->num_kernels; i++) { - struct r600_kernel *kernel = &shader->kernels[i]; - kernel->llvm_module = radeon_llvm_get_kernel_module( - shader->llvm_ctx, i, code, header->num_bytes); - } - } -#else radeon_shader_binary_init(&shader->binary); radeon_elf_read(code, header->num_bytes, &shader->binary); r600_create_shader(&shader->bc, &shader->binary, &use_kill); @@ -235,7 +218,6 @@ void *evergreen_create_compute_state( memcpy(p, shader->bc.bytecode, shader->bc.ndw * 4); ctx->b.ws->buffer_unmap(shader->code_bo->buf); #endif -#endif shader->ctx = ctx; shader->local_size = cso->req_local_mem; @@ -255,21 +237,12 @@ void evergreen_delete_compute_state(struct pipe_context *ctx_, void* state) return; #ifdef HAVE_OPENCL -#if HAVE_LLVM < 0x0306 - for (unsigned i = 0; i < shader->num_kernels; i++) { - struct r600_kernel *kernel = &shader->kernels[i]; - LLVMDisposeModule(module); - } - FREE(shader->kernels); - LLVMContextDispose(shader->llvm_ctx); -#else radeon_shader_binary_clean(&shader->binary); r600_destroy_shader(&shader->bc); /* TODO destroy shader->code_bo, shader->const_bo * we'll need something like r600_buffer_free */ #endif -#endif FREE(shader); } @@ -372,11 +345,7 @@ static void evergreen_emit_direct_dispatch( int group_size = 1; int grid_size = 1; unsigned lds_size = shader->local_size / 4 + -#if HAVE_LLVM < 0x0306 - shader->active_kernel->bc.nlds_dw; -#else shader->bc.nlds_dw; -#endif /* Calculate group_size/grid_size */ @@ -565,18 +534,10 @@ void evergreen_emit_cs_shader( struct r600_resource *code_bo; unsigned ngpr, nstack; -#if HAVE_LLVM < 0x0306 - struct r600_kernel *kernel = &shader->kernels[state->kernel_index]; - code_bo = kernel->code_bo; - va = kernel->code_bo->gpu_address; - ngpr = kernel->bc.ngpr; - nstack = kernel->bc.nstack; -#else code_bo = shader->code_bo; va = shader->code_bo->gpu_address + state->pc; ngpr = shader->bc.ngpr; nstack = shader->bc.nstack; -#endif radeon_compute_set_context_reg_seq(cs, R_0288D0_SQ_PGM_START_LS, 3); radeon_emit(cs, va >> 8); /* R_0288D0_SQ_PGM_START_LS */ @@ -601,46 +562,10 @@ static void evergreen_launch_grid( struct r600_pipe_compute *shader = ctx->cs_shader_state.shader; boolean use_kill; -#if HAVE_LLVM < 0x0306 - struct r600_kernel *kernel = &shader->kernels[pc]; - (void)use_kill; - if (!kernel->code_bo) { - void *p; - struct r600_bytecode *bc = &kernel->bc; - LLVMModuleRef mod = kernel->llvm_module; - boolean use_kill = false; - bool dump = (ctx->screen->b.debug_flags & DBG_CS) != 0; - unsigned use_sb = ctx->screen->b.debug_flags & DBG_SB_CS; - unsigned sb_disasm = use_sb || - (ctx->screen->b.debug_flags & DBG_SB_DISASM); - - r600_bytecode_init(bc, ctx->b.chip_class, ctx->b.family, - ctx->screen->has_compressed_msaa_texturing); - bc->type = TGSI_PROCESSOR_COMPUTE; - bc->isa = ctx->isa; - r600_llvm_compile(mod, ctx->b.family, bc, &use_kill, dump, &ctx->b.debug); - - if (dump && !sb_disasm) { - r600_bytecode_disasm(bc); - } else if ((dump && sb_disasm) || use_sb) { - if (r600_sb_bytecode_process(ctx, bc, NULL, dump, use_sb)) - R600_ERR("r600_sb_bytecode_process failed!\n"); - } - - kernel->code_bo = r600_compute_buffer_alloc_vram(ctx->screen, - kernel->bc.ndw * 4); - p = r600_buffer_map_sync_with_rings(&ctx->b, kernel->code_bo, PIPE_TRANSFER_WRITE); - memcpy(p, kernel->bc.bytecode, kernel->bc.ndw * 4); - ctx->b.ws->buffer_unmap(kernel->code_bo->buf); - } - shader->active_kernel = kernel; - ctx->cs_shader_state.kernel_index = pc; -#else ctx->cs_shader_state.pc = pc; /* Get the config information for this kernel. */ r600_shader_binary_read_config(&shader->binary, &shader->bc, pc, &use_kill); #endif -#endif COMPUTE_DBG(ctx->screen, "*** evergreen_launch_grid: pc = %u\n", pc); diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.h b/src/gallium/drivers/r600/evergreen_compute_internal.h index 95593dd8e13..c8998d00f5a 100644 --- a/src/gallium/drivers/r600/evergreen_compute_internal.h +++ b/src/gallium/drivers/r600/evergreen_compute_internal.h @@ -27,28 +27,9 @@ #include "r600_asm.h" -#if HAVE_LLVM < 0x0306 - -struct r600_kernel { - unsigned count; -#ifdef HAVE_OPENCL - LLVMModuleRef llvm_module; -#endif - struct r600_resource *code_bo; - struct r600_bytecode bc; -}; - -#endif - struct r600_pipe_compute { struct r600_context *ctx; -#if HAVE_LLVM < 0x0306 - unsigned num_kernels; - struct r600_kernel *kernels; - struct r600_kernel *active_kernel; -#endif - struct radeon_shader_binary binary; struct r600_resource *code_bo; struct r600_bytecode bc; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index 9d378013be0..c8580d807d7 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -528,11 +528,7 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e return 16; case PIPE_SHADER_CAP_PREFERRED_IR: if (shader == PIPE_SHADER_COMPUTE) { -#if HAVE_LLVM < 0x0306 - return PIPE_SHADER_IR_LLVM; -#else return PIPE_SHADER_IR_NATIVE; -#endif } else { return PIPE_SHADER_IR_TGSI; } diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index d75317b1cbe..324d2719f44 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -613,7 +613,7 @@ static int r600_get_compute_param(struct pipe_screen *screen, case PIPE_COMPUTE_CAP_IR_TARGET: { const char *gpu; const char *triple; - if (rscreen->family <= CHIP_ARUBA || HAVE_LLVM < 0x0306) { + if (rscreen->family <= CHIP_ARUBA) { triple = "r600--"; } else { triple = "amdgcn--"; @@ -622,11 +622,6 @@ static int r600_get_compute_param(struct pipe_screen *screen, /* Clang < 3.6 is missing Hainan in its list of * GPUs, so we need to use the name of a similar GPU. */ -#if HAVE_LLVM < 0x0306 - case CHIP_HAINAN: - gpu = "oland"; - break; -#endif default: gpu = r600_get_llvm_processor_name(rscreen->family); break; diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index 4d27e86b414..7370a113d3d 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -45,12 +45,6 @@ struct si_compute { struct r600_resource *input_buffer; struct pipe_resource *global_buffers[MAX_GLOBAL_BUFFERS]; - -#if HAVE_LLVM < 0x0306 - unsigned num_kernels; - struct si_shader *kernels; - LLVMContextRef llvm_ctx; -#endif }; static void init_scratch_buffer(struct si_context *sctx, struct si_compute *program) @@ -111,29 +105,6 @@ static void *si_create_compute_state( program->private_size = cso->req_private_mem; program->input_size = cso->req_input_mem; -#if HAVE_LLVM < 0x0306 - { - unsigned i; - program->llvm_ctx = LLVMContextCreate(); - program->num_kernels = radeon_llvm_get_num_kernels(program->llvm_ctx, - code, header->num_bytes); - program->kernels = CALLOC(sizeof(struct si_shader), - program->num_kernels); - for (i = 0; i < program->num_kernels; i++) { - LLVMModuleRef mod = radeon_llvm_get_kernel_module(program->llvm_ctx, i, - code, header->num_bytes); - si_compile_llvm(sctx->screen, &program->kernels[i].binary, - &program->kernels[i].config, sctx->tm, - mod, &sctx->b.debug, TGSI_PROCESSOR_COMPUTE, - "Compute Shader"); - si_shader_dump(sctx->screen, &program->kernels[i], - &sctx->b.debug, TGSI_PROCESSOR_COMPUTE); - si_shader_binary_upload(sctx->screen, &program->kernels[i]); - LLVMDisposeModule(mod); - } - } -#else - radeon_elf_read(code, header->num_bytes, &program->shader.binary); /* init_scratch_buffer patches the shader code with the scratch address, @@ -147,7 +118,6 @@ static void *si_create_compute_state( TGSI_PROCESSOR_COMPUTE); si_shader_binary_upload(sctx->screen, &program->shader); -#endif program->input_buffer = si_resource_create_custom(sctx->b.b.screen, PIPE_USAGE_IMMUTABLE, program->input_size); @@ -247,11 +217,6 @@ static void si_launch_grid( unsigned lds_blocks; unsigned num_waves_for_scratch; -#if HAVE_LLVM < 0x0306 - shader = &program->kernels[pc]; -#endif - - radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0) | PKT3_SHADER_TYPE_S(1)); radeon_emit(cs, 0x80000000); radeon_emit(cs, 0x80000000); @@ -266,10 +231,8 @@ static void si_launch_grid( pm4->compute_pkt = true; -#if HAVE_LLVM >= 0x0306 /* Read the config information */ si_shader_binary_read_config(&shader->binary, &shader->config, pc); -#endif /* Upload the kernel arguments */ @@ -360,10 +323,8 @@ static void si_launch_grid( } shader_va = shader->bo->gpu_address; - -#if HAVE_LLVM >= 0x0306 shader_va += pc; -#endif + radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER); si_pm4_set_reg(pm4, R_00B830_COMPUTE_PGM_LO, shader_va >> 8); @@ -448,26 +409,9 @@ static void si_delete_compute_state(struct pipe_context *ctx, void* state){ return; } -#if HAVE_LLVM < 0x0306 - if (program->kernels) { - for (int i = 0; i < program->num_kernels; i++){ - if (program->kernels[i].bo){ - si_shader_destroy(&program->kernels[i]); - } - } - FREE(program->kernels); - } - - if (program->llvm_ctx){ - LLVMContextDispose(program->llvm_ctx); - } -#else si_shader_destroy(&program->shader); -#endif - pipe_resource_reference( (struct pipe_resource **)&program->input_buffer, NULL); - FREE(program); } diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 34cc06fc078..345f2bbc381 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -203,7 +203,8 @@ static void si_set_sampler_view(struct si_context *sctx, pipe_sampler_view_reference(&views->views[slot], view); memcpy(views->desc.list + slot * 16, rview->state, 8*4); - if (rtex && rtex->fmask.size) { + if (view->texture && view->texture->target != PIPE_BUFFER && + rtex->fmask.size) { memcpy(views->desc.list + slot*16 + 8, rview->fmask_state, 8*4); } else { diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 61ce976c32c..e9d69d2db38 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -74,9 +74,7 @@ static void si_destroy_context(struct pipe_context *context) r600_common_context_cleanup(&sctx->b); -#if HAVE_LLVM >= 0x0306 LLVMDisposeTargetMachine(sctx->tm); -#endif r600_resource_reference(&sctx->trace_buf, NULL); r600_resource_reference(&sctx->last_trace_buf, NULL); @@ -104,9 +102,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, struct si_screen* sscreen = (struct si_screen *)screen; struct radeon_winsys *ws = sscreen->b.ws; LLVMTargetRef r600_target; -#if HAVE_LLVM >= 0x0306 const char *triple = "amdgcn--"; -#endif int shader, i; if (!sctx) @@ -210,7 +206,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, */ sctx->scratch_waves = 32 * sscreen->b.info.num_good_compute_units; -#if HAVE_LLVM >= 0x0306 /* Initialize LLVM TargetMachine */ r600_target = radeon_llvm_get_r600_target(triple); sctx->tm = LLVMCreateTargetMachine(r600_target, triple, @@ -223,7 +218,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen, LLVMCodeGenLevelDefault, LLVMRelocDefault, LLVMCodeModelDefault); -#endif return &sctx->b.b; fail: @@ -310,6 +304,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_INVALIDATE_BUFFER: case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: case PIPE_CAP_QUERY_MEMORY_INFO: + case PIPE_CAP_TGSI_PACK_HALF_FLOAT: return 1; case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: @@ -335,9 +330,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: return 4; - case PIPE_CAP_TGSI_PACK_HALF_FLOAT: - return HAVE_LLVM >= 0x0306; - case PIPE_CAP_GLSL_FEATURE_LEVEL: return HAVE_LLVM >= 0x0307 ? 410 : 330; @@ -449,18 +441,13 @@ static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enu case PIPE_SHADER_TESS_CTRL: case PIPE_SHADER_TESS_EVAL: /* LLVM 3.6.2 is required for tessellation because of bug fixes there */ - if (HAVE_LLVM < 0x0306 || - (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)) + if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2) return 0; break; case PIPE_SHADER_COMPUTE: switch (param) { case PIPE_SHADER_CAP_PREFERRED_IR: -#if HAVE_LLVM < 0x0306 - return PIPE_SHADER_IR_LLVM; -#else return PIPE_SHADER_IR_NATIVE; -#endif case PIPE_SHADER_CAP_DOUBLES: return HAVE_LLVM >= 0x0307; diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 34b84eb81d9..baa1090e2fb 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -67,6 +67,7 @@ struct si_shader_context struct radeon_llvm_context radeon_bld; struct si_shader *shader; struct si_screen *screen; + unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */ bool is_gs_copy_shader; int param_streamout_config; @@ -81,7 +82,9 @@ struct si_shader_context int param_tes_rel_patch_id; int param_tes_patch_id; int param_es2gs_offset; + LLVMTargetMachineRef tm; + LLVMValueRef const_md; LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS]; LLVMValueRef lds; @@ -93,14 +96,31 @@ struct si_shader_context LLVMValueRef esgs_ring; LLVMValueRef gsvs_ring[4]; LLVMValueRef gs_next_vertex[4]; + + LLVMTypeRef voidt; + LLVMTypeRef i1; + LLVMTypeRef i8; + LLVMTypeRef i32; + LLVMTypeRef i128; + LLVMTypeRef f32; + LLVMTypeRef v16i8; + LLVMTypeRef v4i32; + LLVMTypeRef v4f32; + LLVMTypeRef v8i32; }; -static struct si_shader_context * si_shader_context( - struct lp_build_tgsi_context * bld_base) +static struct si_shader_context *si_shader_context( + struct lp_build_tgsi_context *bld_base) { return (struct si_shader_context *)bld_base; } +static void si_init_shader_ctx(struct si_shader_context *ctx, + struct si_screen *sscreen, + struct si_shader *shader, + LLVMTargetMachineRef tm, + struct tgsi_shader_info *info); + #define PERSPECTIVE_BASE 0 #define LINEAR_BASE 9 @@ -168,12 +188,12 @@ unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index) /** * Get the value of a shader input parameter and extract a bitfield. */ -static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx, +static LLVMValueRef unpack_param(struct si_shader_context *ctx, unsigned param, unsigned rshift, unsigned bitwidth) { - struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm; - LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn, param); if (rshift) @@ -189,15 +209,15 @@ static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx, return value; } -static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx) +static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx) { - switch (si_shader_ctx->type) { + switch (ctx->type) { case TGSI_PROCESSOR_TESS_CTRL: - return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8); + return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8); case TGSI_PROCESSOR_TESS_EVAL: - return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, - si_shader_ctx->param_tes_rel_patch_id); + return LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_tes_rel_patch_id); default: assert(0); @@ -227,12 +247,12 @@ static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx) */ static LLVMValueRef -get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx) +get_tcs_in_patch_stride(struct si_shader_context *ctx) { - if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) - return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13); - else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL) - return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13); + if (ctx->type == TGSI_PROCESSOR_VERTEX) + return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13); + else if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) + return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13); else { assert(0); return NULL; @@ -240,48 +260,48 @@ get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx) } static LLVMValueRef -get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx) +get_tcs_out_patch_stride(struct si_shader_context *ctx) { - return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13); + return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13); } static LLVMValueRef -get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx) +get_tcs_out_patch0_offset(struct si_shader_context *ctx) { - return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld, - unpack_param(si_shader_ctx, + return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld, + unpack_param(ctx, SI_PARAM_TCS_OUT_OFFSETS, 0, 16), 4); } static LLVMValueRef -get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx) +get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx) { - return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld, - unpack_param(si_shader_ctx, + return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld, + unpack_param(ctx, SI_PARAM_TCS_OUT_OFFSETS, 16, 16), 4); } static LLVMValueRef -get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx) +get_tcs_in_current_patch_offset(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm; - LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx); - LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx); + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx); + LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, ""); } static LLVMValueRef -get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx) +get_tcs_out_current_patch_offset(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm; - LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx); - LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx); - LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx); + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx); + LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx); + LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); return LLVMBuildAdd(gallivm->builder, patch0_offset, LLVMBuildMul(gallivm->builder, patch_stride, @@ -290,13 +310,13 @@ get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx) } static LLVMValueRef -get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx) +get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm; + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; LLVMValueRef patch0_patch_data_offset = - get_tcs_out_patch0_patch_data_offset(si_shader_ctx); - LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx); - LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx); + get_tcs_out_patch0_patch_data_offset(ctx); + LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx); + LLVMValueRef rel_patch_id = get_rel_patch_id(ctx); return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset, LLVMBuildMul(gallivm->builder, patch_stride, @@ -304,11 +324,11 @@ get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx) ""); } -static void build_indexed_store(struct si_shader_context *si_shader_ctx, +static void build_indexed_store(struct si_shader_context *ctx, LLVMValueRef base_ptr, LLVMValueRef index, LLVMValueRef value) { - struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base; + struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef indices[2], pointer; @@ -326,10 +346,10 @@ static void build_indexed_store(struct si_shader_context *si_shader_ctx, * \param base_ptr Where the array starts. * \param index The element index into the array. */ -static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx, +static LLVMValueRef build_indexed_load(struct si_shader_context *ctx, LLVMValueRef base_ptr, LLVMValueRef index) { - struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base; + struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef indices[2], pointer; @@ -345,24 +365,24 @@ static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx, * a constant. */ static LLVMValueRef build_indexed_load_const( - struct si_shader_context * si_shader_ctx, + struct si_shader_context *ctx, LLVMValueRef base_ptr, LLVMValueRef index) { - LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index); - LLVMSetMetadata(result, 1, si_shader_ctx->const_md); + LLVMValueRef result = build_indexed_load(ctx, base_ptr, index); + LLVMSetMetadata(result, 1, ctx->const_md); return result; } static LLVMValueRef get_instance_index_for_fetch( - struct radeon_llvm_context * radeon_bld, + struct radeon_llvm_context *radeon_bld, unsigned divisor) { - struct si_shader_context *si_shader_ctx = + struct si_shader_context *ctx = si_shader_context(&radeon_bld->soa.bld_base); - struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm; LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn, - si_shader_ctx->param_instance_id); + ctx->param_instance_id); /* The division must be done before START_INSTANCE is added. */ if (divisor > 1) @@ -380,9 +400,9 @@ static void declare_input_vs( { struct lp_build_context *base = &radeon_bld->soa.bld_base.base; struct gallivm_state *gallivm = base->gallivm; - struct si_shader_context *si_shader_ctx = + struct si_shader_context *ctx = si_shader_context(&radeon_bld->soa.bld_base); - unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index]; + unsigned divisor = ctx->shader->key.vs.instance_divisors[input_index]; unsigned chan; @@ -392,38 +412,36 @@ static void declare_input_vs( LLVMValueRef attribute_offset; LLVMValueRef buffer_index; LLVMValueRef args[3]; - LLVMTypeRef vec4_type; LLVMValueRef input; /* Load the T list */ - t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS); + t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS); t_offset = lp_build_const_int32(gallivm, input_index); - t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset); + t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset); /* Build the attribute offset */ attribute_offset = lp_build_const_int32(gallivm, 0); if (divisor) { /* Build index from instance ID, start instance and divisor */ - si_shader_ctx->shader->uses_instanceid = true; - buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor); + ctx->shader->uses_instanceid = true; + buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld, divisor); } else { /* Load the buffer index for vertices. */ - LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, - si_shader_ctx->param_vertex_id); + LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_vertex_id); LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BASE_VERTEX); buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, ""); } - vec4_type = LLVMVectorType(base->elem_type, 4); args[0] = t_list; args[1] = attribute_offset; args[2] = buffer_index; input = lp_build_intrinsic(gallivm->builder, - "llvm.SI.vs.load.input", vec4_type, args, 3, + "llvm.SI.vs.load.input", ctx->v4f32, args, 3, LLVMReadNoneAttribute | LLVMNoUnwindAttribute); /* Break up the vec4 into individual components */ @@ -431,7 +449,7 @@ static void declare_input_vs( LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan); /* XXX: Use a helper function for this. There is one in * tgsi_llvm.c. */ - si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] = + ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] = LLVMBuildExtractElement(gallivm->builder, input, llvm_chan, ""); } @@ -440,23 +458,23 @@ static void declare_input_vs( static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base, unsigned swizzle) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); if (swizzle > 0) return bld_base->uint_bld.zero; - switch (si_shader_ctx->type) { + switch (ctx->type) { case TGSI_PROCESSOR_VERTEX: - return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, - si_shader_ctx->param_vs_prim_id); + return LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_vs_prim_id); case TGSI_PROCESSOR_TESS_CTRL: - return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + return LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PATCH_ID); case TGSI_PROCESSOR_TESS_EVAL: - return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, - si_shader_ctx->param_tes_patch_id); + return LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_tes_patch_id); case TGSI_PROCESSOR_GEOMETRY: - return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + return LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIMITIVE_ID); default: assert(0); @@ -468,14 +486,14 @@ static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base, * Return the value of tgsi_ind_register for indexing. * This is the indirect index with the constant offset added to it. */ -static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx, +static LLVMValueRef get_indirect_index(struct si_shader_context *ctx, const struct tgsi_ind_register *ind, int rel_index) { - struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; LLVMValueRef result; - result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle]; + result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle]; result = LLVMBuildLoad(gallivm->builder, result, ""); result = LLVMBuildAdd(gallivm->builder, result, lp_build_const_int32(gallivm, rel_index), ""); @@ -485,14 +503,14 @@ static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx, /** * Calculate a dword address given an input or output register and a stride. */ -static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx, +static LLVMValueRef get_dw_address(struct si_shader_context *ctx, const struct tgsi_full_dst_register *dst, const struct tgsi_full_src_register *src, LLVMValueRef vertex_dw_stride, LLVMValueRef base_addr) { - struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm; - struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info; + struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; + struct tgsi_shader_info *info = &ctx->shader->selector->info; ubyte *name, *index, *array_first; int first, param; struct tgsi_full_dst_register reg; @@ -516,7 +534,7 @@ static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx, LLVMValueRef index; if (reg.Dimension.Indirect) - index = get_indirect_index(si_shader_ctx, ®.DimIndirect, + index = get_indirect_index(ctx, ®.DimIndirect, reg.Dimension.Index); else index = lp_build_const_int32(gallivm, reg.Dimension.Index); @@ -549,7 +567,7 @@ static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx, else first = reg.Register.Index; - ind_index = get_indirect_index(si_shader_ctx, ®.Indirect, + ind_index = get_indirect_index(ctx, ®.Indirect, reg.Register.Index - first); base_addr = LLVMBuildAdd(gallivm->builder, base_addr, @@ -578,7 +596,7 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base, enum tgsi_opcode_type type, unsigned swizzle, LLVMValueRef dw_addr) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef value; @@ -595,12 +613,12 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base, dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr, lp_build_const_int32(gallivm, swizzle)); - value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr); + value = build_indexed_load(ctx, ctx->lds, dw_addr); if (type == TGSI_TYPE_DOUBLE) { LLVMValueRef value2; dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr, lp_build_const_int32(gallivm, swizzle + 1)); - value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr); + value2 = build_indexed_load(ctx, ctx->lds, dw_addr); return radeon_llvm_emit_fetch_double(bld_base, value, value2); } @@ -615,19 +633,18 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base, * \param dw_addr address in dwords * \param value value to store */ -static void lds_store(struct lp_build_tgsi_context * bld_base, +static void lds_store(struct lp_build_tgsi_context *bld_base, unsigned swizzle, LLVMValueRef dw_addr, LLVMValueRef value) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr, lp_build_const_int32(gallivm, swizzle)); - value = LLVMBuildBitCast(gallivm->builder, value, - LLVMInt32TypeInContext(gallivm->context), ""); - build_indexed_store(si_shader_ctx, si_shader_ctx->lds, + value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, ""); + build_indexed_store(ctx, ctx->lds, dw_addr, value); } @@ -636,12 +653,12 @@ static LLVMValueRef fetch_input_tcs( const struct tgsi_full_src_register *reg, enum tgsi_opcode_type type, unsigned swizzle) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); LLVMValueRef dw_addr, stride; - stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8); - dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx); - dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr); + stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8); + dw_addr = get_tcs_in_current_patch_offset(ctx); + dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr); return lds_load(bld_base, type, swizzle, dw_addr); } @@ -651,16 +668,16 @@ static LLVMValueRef fetch_output_tcs( const struct tgsi_full_src_register *reg, enum tgsi_opcode_type type, unsigned swizzle) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); LLVMValueRef dw_addr, stride; if (reg->Register.Dimension) { - stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8); - dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx); - dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr); + stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8); + dw_addr = get_tcs_out_current_patch_offset(ctx); + dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr); } else { - dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx); - dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr); + dw_addr = get_tcs_out_current_patch_data_offset(ctx); + dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr); } return lds_load(bld_base, type, swizzle, dw_addr); @@ -671,27 +688,27 @@ static LLVMValueRef fetch_input_tes( const struct tgsi_full_src_register *reg, enum tgsi_opcode_type type, unsigned swizzle) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); LLVMValueRef dw_addr, stride; if (reg->Register.Dimension) { - stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8); - dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx); - dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr); + stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8); + dw_addr = get_tcs_out_current_patch_offset(ctx); + dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr); } else { - dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx); - dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr); + dw_addr = get_tcs_out_current_patch_data_offset(ctx); + dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr); } return lds_load(bld_base, type, swizzle, dw_addr); } -static void store_output_tcs(struct lp_build_tgsi_context * bld_base, - const struct tgsi_full_instruction * inst, - const struct tgsi_opcode_info * info, +static void store_output_tcs(struct lp_build_tgsi_context *bld_base, + const struct tgsi_full_instruction *inst, + const struct tgsi_opcode_info *info, LLVMValueRef dst[4]) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); const struct tgsi_full_dst_register *reg = &inst->Dst[0]; unsigned chan_index; LLVMValueRef dw_addr, stride; @@ -706,12 +723,12 @@ static void store_output_tcs(struct lp_build_tgsi_context * bld_base, } if (reg->Register.Dimension) { - stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8); - dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx); - dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr); + stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8); + dw_addr = get_tcs_out_current_patch_offset(ctx); + dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr); } else { - dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx); - dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr); + dw_addr = get_tcs_out_current_patch_data_offset(ctx); + dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr); } TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) { @@ -731,11 +748,10 @@ static LLVMValueRef fetch_input_gs( unsigned swizzle) { struct lp_build_context *base = &bld_base->base; - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); - struct si_shader *shader = si_shader_ctx->shader; - struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld; + struct si_shader_context *ctx = si_shader_context(bld_base); + struct si_shader *shader = ctx->shader; + struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld; struct gallivm_state *gallivm = base->gallivm; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); LLVMValueRef vtx_offset; LLVMValueRef args[9]; unsigned vtx_offset_param; @@ -770,12 +786,12 @@ static LLVMValueRef fetch_input_gs( vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2; } vtx_offset = lp_build_mul_imm(uint, - LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + LLVMGetParam(ctx->radeon_bld.main_fn, vtx_offset_param), 4); param = si_shader_io_get_unique_index(semantic_name, semantic_index); - args[0] = si_shader_ctx->esgs_ring; + args[0] = ctx->esgs_ring; args[1] = vtx_offset; args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256); args[3] = uint->zero; @@ -787,14 +803,14 @@ static LLVMValueRef fetch_input_gs( value = lp_build_intrinsic(gallivm->builder, "llvm.SI.buffer.load.dword.i32.i32", - i32, args, 9, + ctx->i32, args, 9, LLVMReadOnlyAttribute | LLVMNoUnwindAttribute); if (type == TGSI_TYPE_DOUBLE) { LLVMValueRef value2; args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256); value2 = lp_build_intrinsic(gallivm->builder, "llvm.SI.buffer.load.dword.i32.i32", - i32, args, 9, + ctx->i32, args, 9, LLVMReadOnlyAttribute | LLVMNoUnwindAttribute); return radeon_llvm_emit_fetch_double(bld_base, value, value2); @@ -834,10 +850,10 @@ static int lookup_interp_param_index(unsigned interpolate, unsigned location) } /* This shouldn't be used by explicit INTERP opcodes. */ -static unsigned select_interp_param(struct si_shader_context *si_shader_ctx, +static unsigned select_interp_param(struct si_shader_context *ctx, unsigned param) { - if (!si_shader_ctx->shader->key.ps.force_persample_interp) + if (!ctx->shader->key.ps.force_persample_interp) return param; /* If the shader doesn't use center/centroid, just return the parameter. @@ -862,7 +878,7 @@ static unsigned select_interp_param(struct si_shader_context *si_shader_ctx, /** * Interpolate a fragment shader input. * - * @param si_shader_ctx context + * @param ctx context * @param input_index index of the input in hardware * @param semantic_name TGSI_SEMANTIC_* * @param semantic_index semantic index @@ -873,7 +889,7 @@ static unsigned select_interp_param(struct si_shader_context *si_shader_ctx, * @param face SI_PARAM_FRONT_FACE * @param result the return value (4 components) */ -static void interp_fs_input(struct si_shader_context *si_shader_ctx, +static void interp_fs_input(struct si_shader_context *ctx, unsigned input_index, unsigned semantic_name, unsigned semantic_index, @@ -884,11 +900,10 @@ static void interp_fs_input(struct si_shader_context *si_shader_ctx, LLVMValueRef face, LLVMValueRef result[4]) { - struct lp_build_context *base = &si_shader_ctx->radeon_bld.soa.bld_base.base; - struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld; + struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base; + struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld; struct gallivm_state *gallivm = base->gallivm; - LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context); - const char * intr_name; + const char *intr_name; LLVMValueRef attr_number; unsigned chan; @@ -908,7 +923,7 @@ static void interp_fs_input(struct si_shader_context *si_shader_ctx, intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant"; if (semantic_name == TGSI_SEMANTIC_COLOR && - si_shader_ctx->shader->key.ps.color_two_side) { + ctx->shader->key.ps.color_two_side) { LLVMValueRef args[4]; LLVMValueRef is_face_positive; LLVMValueRef back_attr_number; @@ -934,12 +949,12 @@ static void interp_fs_input(struct si_shader_context *si_shader_ctx, args[0] = llvm_chan; args[1] = attr_number; front = lp_build_intrinsic(gallivm->builder, intr_name, - input_type, args, args[3] ? 4 : 3, + ctx->f32, args, args[3] ? 4 : 3, LLVMReadNoneAttribute | LLVMNoUnwindAttribute); args[1] = back_attr_number; back = lp_build_intrinsic(gallivm->builder, intr_name, - input_type, args, args[3] ? 4 : 3, + ctx->f32, args, args[3] ? 4 : 3, LLVMReadNoneAttribute | LLVMNoUnwindAttribute); result[chan] = LLVMBuildSelect(gallivm->builder, @@ -956,7 +971,7 @@ static void interp_fs_input(struct si_shader_context *si_shader_ctx, args[2] = prim_mask; args[3] = interp_param; result[0] = lp_build_intrinsic(gallivm->builder, intr_name, - input_type, args, args[3] ? 4 : 3, + ctx->f32, args, args[3] ? 4 : 3, LLVMReadNoneAttribute | LLVMNoUnwindAttribute); result[1] = result[2] = lp_build_const_float(gallivm, 0.0f); @@ -971,7 +986,7 @@ static void interp_fs_input(struct si_shader_context *si_shader_ctx, args[2] = prim_mask; args[3] = interp_param; result[chan] = lp_build_intrinsic(gallivm->builder, intr_name, - input_type, args, args[3] ? 4 : 3, + ctx->f32, args, args[3] ? 4 : 3, LLVMReadNoneAttribute | LLVMNoUnwindAttribute); } } @@ -982,9 +997,9 @@ static void declare_input_fs( unsigned input_index, const struct tgsi_full_declaration *decl) { - struct si_shader_context *si_shader_ctx = + struct si_shader_context *ctx = si_shader_context(&radeon_bld->soa.bld_base); - struct si_shader *shader = si_shader_ctx->shader; + struct si_shader *shader = ctx->shader; LLVMValueRef main_fn = radeon_bld->main_fn; LLVMValueRef interp_param = NULL; int interp_param_idx; @@ -994,12 +1009,12 @@ static void declare_input_fs( if (interp_param_idx == -1) return; else if (interp_param_idx) { - interp_param_idx = select_interp_param(si_shader_ctx, + interp_param_idx = select_interp_param(ctx, interp_param_idx); interp_param = LLVMGetParam(main_fn, interp_param_idx); } - interp_fs_input(si_shader_ctx, input_index, decl->Semantic.Name, + interp_fs_input(ctx, input_index, decl->Semantic.Name, decl->Semantic.Index, shader->selector->info.num_inputs, shader->selector->info.colors_read, interp_param, LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK), @@ -1027,22 +1042,22 @@ static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resou static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id) { - struct si_shader_context *si_shader_ctx = + struct si_shader_context *ctx = si_shader_context(&radeon_bld->soa.bld_base); struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld; struct gallivm_state *gallivm = &radeon_bld->gallivm; LLVMBuilderRef builder = gallivm->builder; - LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); + LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF); - LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index); + LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index); /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */ LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8); LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), ""); LLVMValueRef pos[4] = { - buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type), - buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type), + buffer_load_const(builder, resource, offset0, ctx->f32), + buffer_load_const(builder, resource, offset1, ctx->f32), lp_build_const_float(gallivm, 0), lp_build_const_float(gallivm, 0) }; @@ -1051,11 +1066,11 @@ static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, } static void declare_system_value( - struct radeon_llvm_context * radeon_bld, + struct radeon_llvm_context *radeon_bld, unsigned index, const struct tgsi_full_declaration *decl) { - struct si_shader_context *si_shader_ctx = + struct si_shader_context *ctx = si_shader_context(&radeon_bld->soa.bld_base); struct lp_build_context *bld = &radeon_bld->soa.bld_base.base; struct gallivm_state *gallivm = &radeon_bld->gallivm; @@ -1064,20 +1079,20 @@ static void declare_system_value( switch (decl->Semantic.Name) { case TGSI_SEMANTIC_INSTANCEID: value = LLVMGetParam(radeon_bld->main_fn, - si_shader_ctx->param_instance_id); + ctx->param_instance_id); break; case TGSI_SEMANTIC_VERTEXID: value = LLVMBuildAdd(gallivm->builder, LLVMGetParam(radeon_bld->main_fn, - si_shader_ctx->param_vertex_id), + ctx->param_vertex_id), LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BASE_VERTEX), ""); break; case TGSI_SEMANTIC_VERTEXID_NOBASE: value = LLVMGetParam(radeon_bld->main_fn, - si_shader_ctx->param_vertex_id); + ctx->param_vertex_id); break; case TGSI_SEMANTIC_BASEVERTEX: @@ -1086,9 +1101,9 @@ static void declare_system_value( break; case TGSI_SEMANTIC_INVOCATIONID: - if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL) - value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5); - else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) + if (ctx->type == TGSI_PROCESSOR_TESS_CTRL) + value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5); + else if (ctx->type == TGSI_PROCESSOR_GEOMETRY) value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GS_INSTANCE_ID); else @@ -1142,14 +1157,14 @@ static void declare_system_value( case TGSI_SEMANTIC_TESSCOORD: { LLVMValueRef coord[4] = { - LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u), - LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v), + LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u), + LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v), bld->zero, bld->zero }; /* For triangles, the vector should be (u, v, 1-u-v). */ - if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == + if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_TRIANGLES) coord[2] = lp_build_sub(bld, bld->one, lp_build_add(bld, coord[0], coord[1])); @@ -1159,7 +1174,7 @@ static void declare_system_value( } case TGSI_SEMANTIC_VERTICESIN: - value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6); + value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6); break; case TGSI_SEMANTIC_TESSINNER: @@ -1168,7 +1183,7 @@ static void declare_system_value( LLVMValueRef dw_addr; int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0); - dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx); + dw_addr = get_tcs_out_current_patch_data_offset(ctx); dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr, lp_build_const_int32(gallivm, param * 4), ""); @@ -1190,13 +1205,13 @@ static void declare_system_value( } static LLVMValueRef fetch_constant( - struct lp_build_tgsi_context * bld_base, + struct lp_build_tgsi_context *bld_base, const struct tgsi_full_src_register *reg, enum tgsi_opcode_type type, unsigned swizzle) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); - struct lp_build_context * base = &bld_base->base; + struct si_shader_context *ctx = si_shader_context(bld_base); + struct lp_build_context *base = &bld_base->base; const struct tgsi_ind_register *ireg = ®->Indirect; unsigned buf, idx; @@ -1217,44 +1232,44 @@ static LLVMValueRef fetch_constant( if (!reg->Register.Indirect && !reg->Dimension.Indirect) { if (type != TGSI_TYPE_DOUBLE) - return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]); + return bitcast(bld_base, type, ctx->constants[buf][idx]); else { return radeon_llvm_emit_fetch_double(bld_base, - si_shader_ctx->constants[buf][idx], - si_shader_ctx->constants[buf][idx + 1]); + ctx->constants[buf][idx], + ctx->constants[buf][idx + 1]); } } if (reg->Register.Dimension && reg->Dimension.Indirect) { - LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); + LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); LLVMValueRef index; - index = get_indirect_index(si_shader_ctx, ®->DimIndirect, + index = get_indirect_index(ctx, ®->DimIndirect, reg->Dimension.Index); - bufp = build_indexed_load_const(si_shader_ctx, ptr, index); + bufp = build_indexed_load_const(ctx, ptr, index); } else - bufp = si_shader_ctx->const_buffers[buf]; + bufp = ctx->const_buffers[buf]; - addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle]; + addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle]; addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg"); addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16); addr = lp_build_add(&bld_base->uint_bld, addr, lp_build_const_int32(base->gallivm, idx * 4)); result = buffer_load_const(base->gallivm->builder, bufp, - addr, bld_base->base.elem_type); + addr, ctx->f32); if (type != TGSI_TYPE_DOUBLE) result = bitcast(bld_base, type, result); else { LLVMValueRef addr2, result2; - addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1]; + addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1]; addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2"); addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16); addr2 = lp_build_add(&bld_base->uint_bld, addr2, lp_build_const_int32(base->gallivm, idx * 4)); - result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf], - addr2, bld_base->base.elem_type); + result2 = buffer_load_const(base->gallivm->builder, ctx->const_buffers[buf], + addr2, ctx->f32); result = radeon_llvm_emit_fetch_double(bld_base, result, result2); @@ -1290,9 +1305,9 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, unsigned target, LLVMValueRef *args) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *uint = - &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld; + &ctx->radeon_bld.soa.bld_base.uint_bld; struct lp_build_context *base = &bld_base->base; struct gallivm_state *gallivm = base->gallivm; LLVMBuilderRef builder = base->gallivm->builder; @@ -1313,8 +1328,8 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, /* Specify the target we are exporting */ args[3] = lp_build_const_int32(base->gallivm, target); - if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) { - const union si_shader_key *key = &si_shader_ctx->shader->key; + if (ctx->type == TGSI_PROCESSOR_FRAGMENT) { + const union si_shader_key *key = &ctx->shader->key; unsigned col_formats = key->ps.spi_shader_col_format; int cbuf = target - V_008DFC_SQ_EXP_MRT; @@ -1364,11 +1379,11 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, packed = lp_build_intrinsic(base->gallivm->builder, "llvm.SI.packf16", - uint->elem_type, pack_args, 2, + ctx->i32, pack_args, 2, LLVMReadNoneAttribute | LLVMNoUnwindAttribute); args[chan + 5] = LLVMBuildBitCast(base->gallivm->builder, - packed, base->elem_type, ""); + packed, ctx->f32, ""); } break; @@ -1380,7 +1395,7 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, val[chan] = LLVMBuildFAdd(builder, val[chan], lp_build_const_float(gallivm, 0.5), ""); val[chan] = LLVMBuildFPToUI(builder, val[chan], - uint->elem_type, ""); + ctx->i32, ""); } args[4] = uint->one; /* COMPR flag */ @@ -1409,7 +1424,7 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, val[chan], base->zero, ""), lp_build_const_float(gallivm, 0.5), lp_build_const_float(gallivm, -0.5), ""), ""); - val[chan] = LLVMBuildFPToSI(builder, val[chan], uint->elem_type, ""); + val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, ""); } args[4] = uint->one; /* COMPR flag */ @@ -1470,16 +1485,16 @@ static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base, static void si_alpha_test(struct lp_build_tgsi_context *bld_base, LLVMValueRef alpha) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; - if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) { - LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + if (ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) { + LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_ALPHA_REF); LLVMValueRef alpha_pass = lp_build_cmp(&bld_base->base, - si_shader_ctx->shader->key.ps.alpha_func, + ctx->shader->key.ps.alpha_func, alpha, alpha_ref); LLVMValueRef arg = lp_build_select(&bld_base->base, @@ -1487,36 +1502,32 @@ static void si_alpha_test(struct lp_build_tgsi_context *bld_base, lp_build_const_float(gallivm, 1.0f), lp_build_const_float(gallivm, -1.0f)); - lp_build_intrinsic(gallivm->builder, - "llvm.AMDGPU.kill", - LLVMVoidTypeInContext(gallivm->context), - &arg, 1, 0); + lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill", + ctx->voidt, &arg, 1, 0); } else { - lp_build_intrinsic(gallivm->builder, - "llvm.AMDGPU.kilp", - LLVMVoidTypeInContext(gallivm->context), - NULL, 0, 0); + lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp", + ctx->voidt, NULL, 0, 0); } } static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base, LLVMValueRef alpha) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef coverage; /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */ - coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + coverage = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SAMPLE_COVERAGE); coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage); coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32", - bld_base->int_bld.elem_type, + ctx->i32, &coverage, 1, LLVMReadNoneAttribute); coverage = LLVMBuildUIToFP(gallivm->builder, coverage, - bld_base->base.elem_type, ""); + ctx->f32, ""); coverage = LLVMBuildFMul(gallivm->builder, coverage, lp_build_const_float(gallivm, @@ -1525,19 +1536,19 @@ static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context * return LLVMBuildFMul(gallivm->builder, alpha, coverage, ""); } -static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base, +static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base, LLVMValueRef (*pos)[9], LLVMValueRef *out_elts) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *base = &bld_base->base; - struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld; + struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld; unsigned reg_index; unsigned chan; unsigned const_chan; LLVMValueRef base_elt; - LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); + LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF); - LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index); + LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index); for (reg_index = 0; reg_index < 2; reg_index ++) { LLVMValueRef *args = pos[2 + reg_index]; @@ -1554,7 +1565,7 @@ static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base, ((reg_index * 4 + chan) * 4 + const_chan) * 4); base_elt = buffer_load_const(base->gallivm->builder, const_resource, - args[1], base->elem_type); + args[1], ctx->f32); args[5 + chan] = lp_build_add(base, args[5 + chan], lp_build_mul(base, base_elt, @@ -1595,7 +1606,7 @@ static void si_dump_streamout(struct pipe_stream_output_info *so) /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4. * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2), * or v4i32 (num_channels=3,4). */ -static void build_tbuffer_store(struct si_shader_context *shader, +static void build_tbuffer_store(struct si_shader_context *ctx, LLVMValueRef rsrc, LLVMValueRef vdata, unsigned num_channels, @@ -1610,22 +1621,21 @@ static void build_tbuffer_store(struct si_shader_context *shader, unsigned slc, unsigned tfe) { - struct gallivm_state *gallivm = &shader->radeon_bld.gallivm; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; LLVMValueRef args[] = { rsrc, vdata, - LLVMConstInt(i32, num_channels, 0), + LLVMConstInt(ctx->i32, num_channels, 0), vaddr, soffset, - LLVMConstInt(i32, inst_offset, 0), - LLVMConstInt(i32, dfmt, 0), - LLVMConstInt(i32, nfmt, 0), - LLVMConstInt(i32, offen, 0), - LLVMConstInt(i32, idxen, 0), - LLVMConstInt(i32, glc, 0), - LLVMConstInt(i32, slc, 0), - LLVMConstInt(i32, tfe, 0) + LLVMConstInt(ctx->i32, inst_offset, 0), + LLVMConstInt(ctx->i32, dfmt, 0), + LLVMConstInt(ctx->i32, nfmt, 0), + LLVMConstInt(ctx->i32, offen, 0), + LLVMConstInt(ctx->i32, idxen, 0), + LLVMConstInt(ctx->i32, glc, 0), + LLVMConstInt(ctx->i32, slc, 0), + LLVMConstInt(ctx->i32, tfe, 0) }; /* The instruction offset field has 12 bits */ @@ -1637,12 +1647,11 @@ static void build_tbuffer_store(struct si_shader_context *shader, char name[256]; snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]); - lp_build_intrinsic(gallivm->builder, name, - LLVMVoidTypeInContext(gallivm->context), + lp_build_intrinsic(gallivm->builder, name, ctx->voidt, args, Elements(args), 0); } -static void build_tbuffer_store_dwords(struct si_shader_context *shader, +static void build_tbuffer_store_dwords(struct si_shader_context *ctx, LLVMValueRef rsrc, LLVMValueRef vdata, unsigned num_channels, @@ -1658,30 +1667,28 @@ static void build_tbuffer_store_dwords(struct si_shader_context *shader, }; assert(num_channels >= 1 && num_channels <= 4); - build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset, + build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset, inst_offset, dfmt[num_channels-1], V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0); } /* On SI, the vertex shader is responsible for writing streamout data * to buffers. */ -static void si_llvm_emit_streamout(struct si_shader_context *shader, +static void si_llvm_emit_streamout(struct si_shader_context *ctx, struct si_shader_output_values *outputs, unsigned noutput) { - struct pipe_stream_output_info *so = &shader->shader->selector->so; - struct gallivm_state *gallivm = &shader->radeon_bld.gallivm; + struct pipe_stream_output_info *so = &ctx->shader->selector->so; + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; LLVMBuilderRef builder = gallivm->builder; int i, j; struct lp_build_if_state if_ctx; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); - /* Get bits [22:16], i.e. (so_param >> 16) & 127; */ LLVMValueRef so_vtx_count = - unpack_param(shader, shader->param_streamout_config, 16, 7); + unpack_param(ctx, ctx->param_streamout_config, 16, 7); - LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32, + LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", ctx->i32, NULL, 0, LLVMReadNoneAttribute); /* can_emit = tid < so_vtx_count; */ @@ -1689,7 +1696,7 @@ static void si_llvm_emit_streamout(struct si_shader_context *shader, LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, ""); LLVMValueRef stream_id = - unpack_param(shader, shader->param_streamout_config, 24, 2); + unpack_param(ctx, ctx->param_streamout_config, 24, 2); /* Emit the streamout code conditionally. This actually avoids * out-of-bounds buffer access. The hw tells us via the SGPR @@ -1703,8 +1710,8 @@ static void si_llvm_emit_streamout(struct si_shader_context *shader, */ LLVMValueRef so_write_index = - LLVMGetParam(shader->radeon_bld.main_fn, - shader->param_streamout_write_index); + LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_streamout_write_index); /* Compute (streamout_write_index + thread_id). */ so_write_index = LLVMBuildAdd(builder, so_write_index, tid, ""); @@ -1715,12 +1722,12 @@ static void si_llvm_emit_streamout(struct si_shader_context *shader, if (!so->stride[i]) continue; - LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn, - shader->param_streamout_offset[i]); - so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), ""); + LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_streamout_offset[i]); + so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), ""); so_write_offset[i] = LLVMBuildMul(builder, so_write_index, - LLVMConstInt(i32, so->stride[i]*4, 0), ""); + LLVMConstInt(ctx->i32, so->stride[i]*4, 0), ""); so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, ""); } @@ -1745,7 +1752,7 @@ static void si_llvm_emit_streamout(struct si_shader_context *shader, for (j = 0; j < num_comps; j++) { out[j] = LLVMBuildBitCast(builder, outputs[reg].values[start+j], - i32, ""); + ctx->i32, ""); } /* Pack the output. */ @@ -1758,10 +1765,10 @@ static void si_llvm_emit_streamout(struct si_shader_context *shader, case 2: /* as v2i32 */ case 3: /* as v4i32 (aligned to 4) */ case 4: /* as v4i32 */ - vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps))); + vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps))); for (j = 0; j < num_comps; j++) { vdata = LLVMBuildInsertElement(builder, vdata, out[j], - LLVMConstInt(i32, j, 0), ""); + LLVMConstInt(ctx->i32, j, 0), ""); } break; } @@ -1772,10 +1779,10 @@ static void si_llvm_emit_streamout(struct si_shader_context *shader, lp_build_const_int32(gallivm, stream), ""); lp_build_if(&if_ctx_stream, gallivm, can_emit_stream); - build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx], + build_tbuffer_store_dwords(ctx, ctx->so_buffers[buf_idx], vdata, num_comps, so_write_offset[buf_idx], - LLVMConstInt(i32, 0, 0), + LLVMConstInt(ctx->i32, 0, 0), so->output[i].dst_offset*4); lp_build_endif(&if_ctx_stream); } @@ -1789,11 +1796,11 @@ static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base, struct si_shader_output_values *outputs, unsigned noutput) { - struct si_shader_context * si_shader_ctx = si_shader_context(bld_base); - struct si_shader * shader = si_shader_ctx->shader; - struct lp_build_context * base = &bld_base->base; - struct lp_build_context * uint = - &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld; + struct si_shader_context *ctx = si_shader_context(bld_base); + struct si_shader *shader = ctx->shader; + struct lp_build_context *base = &bld_base->base; + struct lp_build_context *uint = + &ctx->radeon_bld.soa.bld_base.uint_bld; LLVMValueRef args[9]; LLVMValueRef pos_args[4][9] = { { 0 } }; LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL; @@ -1803,8 +1810,8 @@ static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base, unsigned pos_idx; int i; - if (outputs && si_shader_ctx->shader->selector->so.num_outputs) { - si_llvm_emit_streamout(si_shader_ctx, outputs, noutput); + if (outputs && ctx->shader->selector->so.num_outputs) { + si_llvm_emit_streamout(ctx, outputs, noutput); } for (i = 0; i < noutput; i++) { @@ -1866,8 +1873,7 @@ handle_semantic: args, sizeof(args)); } else { lp_build_intrinsic(base->gallivm->builder, - "llvm.SI.export", - LLVMVoidTypeInContext(base->gallivm->context), + "llvm.SI.export", ctx->voidt, args, 9, 0); } @@ -1919,7 +1925,7 @@ handle_semantic: * with the first bit containing the edge flag. */ edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder, edgeflag_value, - bld_base->uint_bld.elem_type, ""); + ctx->i32, ""); edgeflag_value = lp_build_min(&bld_base->int_bld, edgeflag_value, bld_base->int_bld.one); @@ -1927,7 +1933,7 @@ handle_semantic: /* The LLVM intrinsic expects a float. */ pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder, edgeflag_value, - base->elem_type, ""); + ctx->f32, ""); } if (shader->selector->info.writes_layer) @@ -1953,10 +1959,8 @@ handle_semantic: /* Specify that this is the last export */ pos_args[i][2] = uint->one; - lp_build_intrinsic(base->gallivm->builder, - "llvm.SI.export", - LLVMVoidTypeInContext(base->gallivm->context), - pos_args[i], 9, 0); + lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export", + ctx->voidt, pos_args[i], 9, 0); } } @@ -1965,9 +1969,9 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base, LLVMValueRef invocation_id, LLVMValueRef tcs_out_current_patch_data_offset) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; - struct si_shader *shader = si_shader_ctx->shader; + struct si_shader *shader = ctx->shader; unsigned tess_inner_index, tess_outer_index; LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer; LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base; @@ -2033,22 +2037,22 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base, vec1 = lp_build_gather_values(gallivm, out+4, stride - 4); /* Get the buffer. */ - rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); - buffer = build_indexed_load_const(si_shader_ctx, rw_buffers, + buffer = build_indexed_load_const(ctx, rw_buffers, lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR)); /* Get the offset. */ - tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + tf_base = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_TESS_FACTOR_OFFSET); byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id, lp_build_const_int32(gallivm, 4 * stride), ""); /* Store the outputs. */ - build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0, + build_tbuffer_store_dwords(ctx, buffer, vec0, MIN2(stride, 4), byteoffset, tf_base, 0); if (vec1) - build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1, + build_tbuffer_store_dwords(ctx, buffer, vec1, stride - 4, byteoffset, tf_base, 16); lp_build_endif(&if_ctx); } @@ -2056,35 +2060,35 @@ static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base, /* This only writes the tessellation factor levels. */ static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); LLVMValueRef invocation_id; - invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5); + invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5); si_write_tess_factors(bld_base, - get_rel_patch_id(si_shader_ctx), + get_rel_patch_id(ctx), invocation_id, - get_tcs_out_current_patch_data_offset(si_shader_ctx)); + get_tcs_out_current_patch_data_offset(ctx)); } -static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base) +static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); - struct si_shader *shader = si_shader_ctx->shader; + struct si_shader_context *ctx = si_shader_context(bld_base); + struct si_shader *shader = ctx->shader; struct tgsi_shader_info *info = &shader->selector->info; struct gallivm_state *gallivm = bld_base->base.gallivm; unsigned i, chan; - LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, - si_shader_ctx->param_rel_auto_id); + LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_rel_auto_id); LLVMValueRef vertex_dw_stride = - unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8); + unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8); LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id, vertex_dw_stride, ""); /* Write outputs to LDS. The next shader (TCS aka HS) will read * its inputs from it. */ for (i = 0; i < info->num_outputs; i++) { - LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i]; + LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i]; unsigned name = info->output_semantic_name[i]; unsigned index = info->output_semantic_index[i]; int param = si_shader_io_get_unique_index(name, index); @@ -2098,21 +2102,20 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base) } } -static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base) +static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; - struct si_shader *es = si_shader_ctx->shader; + struct si_shader *es = ctx->shader; struct tgsi_shader_info *info = &es->selector->info; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); - LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, - si_shader_ctx->param_es2gs_offset); + LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_es2gs_offset); unsigned chan; int i; for (i = 0; i < info->num_outputs; i++) { LLVMValueRef *out_ptr = - si_shader_ctx->radeon_bld.soa.outputs[i]; + ctx->radeon_bld.soa.outputs[i]; int param_index; if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX || @@ -2124,12 +2127,12 @@ static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base) for (chan = 0; chan < 4; chan++) { LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""); - out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, ""); + out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, ""); - build_tbuffer_store(si_shader_ctx, - si_shader_ctx->esgs_ring, + build_tbuffer_store(ctx, + ctx->esgs_ring, out_val, 1, - LLVMGetUndef(i32), soffset, + LLVMGetUndef(ctx->i32), soffset, (4 * param_index + chan) * 4, V_008F0C_BUF_DATA_FORMAT_32, V_008F0C_BUF_NUM_FORMAT_UINT, @@ -2140,26 +2143,25 @@ static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base) static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef args[2]; args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE); - args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); + args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg", - LLVMVoidTypeInContext(gallivm->context), args, 2, - LLVMNoUnwindAttribute); + ctx->voidt, args, 2, LLVMNoUnwindAttribute); } -static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base) +static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; - struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info; + struct tgsi_shader_info *info = &ctx->shader->selector->info; struct si_shader_output_values *outputs = NULL; int i,j; - assert(!si_shader_ctx->is_gs_copy_shader); + assert(!ctx->is_gs_copy_shader); outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0])); @@ -2169,7 +2171,7 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base) * an IF statement is added that clamps all colors if the constant * is true. */ - if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) { + if (ctx->type == TGSI_PROCESSOR_VERTEX) { struct lp_build_if_state if_ctx; LLVMValueRef cond = NULL; LLVMValueRef addr, val; @@ -2182,15 +2184,15 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base) /* We've found a color. */ if (!cond) { /* The state is in the first bit of the user SGPR. */ - cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + cond = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VS_STATE_BITS); cond = LLVMBuildTrunc(gallivm->builder, cond, - LLVMInt1TypeInContext(gallivm->context), ""); + ctx->i1, ""); lp_build_if(&if_ctx, gallivm, cond); } for (j = 0; j < 4; j++) { - addr = si_shader_ctx->radeon_bld.soa.outputs[i][j]; + addr = ctx->radeon_bld.soa.outputs[i][j]; val = LLVMBuildLoad(gallivm->builder, addr, ""); val = radeon_llvm_saturate(bld_base, val); LLVMBuildStore(gallivm->builder, val, addr); @@ -2208,12 +2210,12 @@ static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base) for (j = 0; j < 4; j++) outputs[i].values[j] = LLVMBuildLoad(gallivm->builder, - si_shader_ctx->radeon_bld.soa.outputs[i][j], + ctx->radeon_bld.soa.outputs[i][j], ""); } /* Export PrimitiveID when PS needs it. */ - if (si_vs_exports_prim_id(si_shader_ctx->shader)) { + if (si_vs_exports_prim_id(ctx->shader)) { outputs[i].name = TGSI_SEMANTIC_PRIMID; outputs[i].sid = 0; outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, @@ -2232,7 +2234,7 @@ static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base, LLVMValueRef depth, LLVMValueRef stencil, LLVMValueRef samplemask) { - struct si_screen *sscreen = si_shader_context(bld_base)->screen; + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *base = &bld_base->base; struct lp_build_context *uint = &bld_base->uint_bld; LLVMValueRef args[9]; @@ -2269,51 +2271,50 @@ static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base, /* SI (except OLAND) has a bug that it only looks * at the X writemask component. */ - if (sscreen->b.chip_class == SI && - sscreen->b.family != CHIP_OLAND) + if (ctx->screen->b.chip_class == SI && + ctx->screen->b.family != CHIP_OLAND) mask |= 0x1; /* Specify which components to enable */ args[0] = lp_build_const_int32(base->gallivm, mask); lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export", - LLVMVoidTypeInContext(base->gallivm->context), - args, 9, 0); + ctx->voidt, args, 9, 0); } static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base, LLVMValueRef *color, unsigned index, bool is_last) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *base = &bld_base->base; int i; /* Clamp color */ - if (si_shader_ctx->shader->key.ps.clamp_color) + if (ctx->shader->key.ps.clamp_color) for (i = 0; i < 4; i++) color[i] = radeon_llvm_saturate(bld_base, color[i]); /* Alpha to one */ - if (si_shader_ctx->shader->key.ps.alpha_to_one) + if (ctx->shader->key.ps.alpha_to_one) color[3] = base->one; /* Alpha test */ if (index == 0 && - si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS) + ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS) si_alpha_test(bld_base, color[3]); /* Line & polygon smoothing */ - if (si_shader_ctx->shader->key.ps.poly_line_smoothing) + if (ctx->shader->key.ps.poly_line_smoothing) color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]); /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */ - if (si_shader_ctx->shader->key.ps.last_cbuf > 0) { + if (ctx->shader->key.ps.last_cbuf > 0) { LLVMValueRef args[8][9]; int c, last = -1; /* Get the export arguments, also find out what the last one is. */ - for (c = 0; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) { + for (c = 0; c <= ctx->shader->key.ps.last_cbuf; c++) { si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + c, args[c]); if (args[c][0] != bld_base->uint_bld.zero) @@ -2321,7 +2322,7 @@ static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base, } /* Emit all exports. */ - for (c = 0; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) { + for (c = 0; c <= ctx->shader->key.ps.last_cbuf; c++) { if (is_last && last == c) { args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */ args[c][2] = bld_base->uint_bld.one; /* DONE bit */ @@ -2329,8 +2330,7 @@ static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base, continue; /* unnecessary NULL export */ lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export", - LLVMVoidTypeInContext(base->gallivm->context), - args[c], 9, 0); + ctx->voidt, args[c], 9, 0); } } else { LLVMValueRef args[9]; @@ -2345,13 +2345,13 @@ static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base, return; /* unnecessary NULL export */ lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export", - LLVMVoidTypeInContext(base->gallivm->context), - args, 9, 0); + ctx->voidt, args, 9, 0); } } static void si_export_null(struct lp_build_tgsi_context *bld_base) { + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *base = &bld_base->base; struct lp_build_context *uint = &bld_base->uint_bld; LLVMValueRef args[9]; @@ -2367,15 +2367,14 @@ static void si_export_null(struct lp_build_tgsi_context *bld_base) args[8] = uint->undef; /* A */ lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export", - LLVMVoidTypeInContext(base->gallivm->context), - args, 9, 0); + ctx->voidt, args, 9, 0); } -static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base) +static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base) { - struct si_shader_context * si_shader_ctx = si_shader_context(bld_base); - struct si_shader * shader = si_shader_ctx->shader; - struct lp_build_context * base = &bld_base->base; + struct si_shader_context *ctx = si_shader_context(bld_base); + struct si_shader *shader = ctx->shader; + struct lp_build_context *base = &bld_base->base; struct tgsi_shader_info *info = &shader->selector->info; LLVMBuilderRef builder = base->gallivm->builder; LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL; @@ -2430,20 +2429,20 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base) switch (semantic_name) { case TGSI_SEMANTIC_POSITION: depth = LLVMBuildLoad(builder, - si_shader_ctx->radeon_bld.soa.outputs[i][2], ""); + ctx->radeon_bld.soa.outputs[i][2], ""); break; case TGSI_SEMANTIC_STENCIL: stencil = LLVMBuildLoad(builder, - si_shader_ctx->radeon_bld.soa.outputs[i][1], ""); + ctx->radeon_bld.soa.outputs[i][1], ""); break; case TGSI_SEMANTIC_SAMPLEMASK: samplemask = LLVMBuildLoad(builder, - si_shader_ctx->radeon_bld.soa.outputs[i][0], ""); + ctx->radeon_bld.soa.outputs[i][0], ""); break; case TGSI_SEMANTIC_COLOR: for (j = 0; j < 4; j++) color[j] = LLVMBuildLoad(builder, - si_shader_ctx->radeon_bld.soa.outputs[i][j], ""); + ctx->radeon_bld.soa.outputs[i][j], ""); si_export_mrt_color(bld_base, color, semantic_index, last_color_export == i); @@ -2459,9 +2458,9 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base) si_export_mrt_z(bld_base, depth, stencil, samplemask); } -static void build_tex_intrinsic(const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data); +static void build_tex_intrinsic(const struct lp_build_tgsi_action *action, + struct lp_build_tgsi_context *bld_base, + struct lp_build_emit_data *emit_data); static bool tgsi_is_array_sampler(unsigned target) { @@ -2474,20 +2473,20 @@ static bool tgsi_is_array_sampler(unsigned target) target == TGSI_TEXTURE_2D_ARRAY_MSAA; } -static void set_tex_fetch_args(struct gallivm_state *gallivm, +static void set_tex_fetch_args(struct si_shader_context *ctx, struct lp_build_emit_data *emit_data, unsigned opcode, unsigned target, LLVMValueRef res_ptr, LLVMValueRef samp_ptr, LLVMValueRef *param, unsigned count, unsigned dmask) { + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; unsigned num_args; unsigned is_rect = target == TGSI_TEXTURE_RECT; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); /* Pad to power of two vector */ while (count < util_next_power_of_two(count)) - param[count++] = LLVMGetUndef(i32); + param[count++] = LLVMGetUndef(ctx->i32); /* Texture coordinates. */ if (count > 1) @@ -2500,10 +2499,9 @@ static void set_tex_fetch_args(struct gallivm_state *gallivm, num_args = 2; if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ) - emit_data->dst_type = LLVMVectorType(i32, 4); + emit_data->dst_type = ctx->v4i32; else { - emit_data->dst_type = LLVMVectorType( - LLVMFloatTypeInContext(gallivm->context), 4); + emit_data->dst_type = ctx->v4f32; emit_data->args[num_args++] = samp_ptr; } @@ -2538,44 +2536,43 @@ static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements) /** * Load an image view, fmask view. or sampler state descriptor. */ -static LLVMValueRef get_sampler_desc(struct si_shader_context *si_shader_ctx, +static LLVMValueRef get_sampler_desc(struct si_shader_context *ctx, LLVMValueRef index, enum desc_type type) { - struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; LLVMBuilderRef builder = gallivm->builder; - LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_SAMPLERS); switch (type) { case DESC_IMAGE: /* The image is at [0:7]. */ - index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 2, 0), ""); + index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), ""); break; case DESC_FMASK: /* The FMASK is at [8:15]. */ - index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 2, 0), ""); - index = LLVMBuildAdd(builder, index, LLVMConstInt(i32, 1, 0), ""); + index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), ""); + index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), ""); break; case DESC_SAMPLER: /* The sampler state is at [12:15]. */ - index = LLVMBuildMul(builder, index, LLVMConstInt(i32, 4, 0), ""); - index = LLVMBuildAdd(builder, index, LLVMConstInt(i32, 3, 0), ""); + index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), ""); + index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), ""); ptr = LLVMBuildPointerCast(builder, ptr, - const_array(LLVMVectorType(i32, 4), 0), ""); + const_array(ctx->v4i32, 0), ""); break; } - return build_indexed_load_const(si_shader_ctx, ptr, index); + return build_indexed_load_const(ctx, ptr, index); } static void tex_fetch_ptrs( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data, + struct lp_build_tgsi_context *bld_base, + struct lp_build_emit_data *emit_data, LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); - const struct tgsi_full_instruction * inst = emit_data->inst; + struct si_shader_context *ctx = si_shader_context(bld_base); + const struct tgsi_full_instruction *inst = emit_data->inst; unsigned target = inst->Texture.Texture; unsigned sampler_src; unsigned sampler_index; @@ -2587,33 +2584,33 @@ static void tex_fetch_ptrs( const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src]; LLVMValueRef ind_index; - ind_index = get_indirect_index(si_shader_ctx, ®->Indirect, reg->Register.Index); + ind_index = get_indirect_index(ctx, ®->Indirect, reg->Register.Index); - *res_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_IMAGE); + *res_ptr = get_sampler_desc(ctx, ind_index, DESC_IMAGE); if (target == TGSI_TEXTURE_2D_MSAA || target == TGSI_TEXTURE_2D_ARRAY_MSAA) { *samp_ptr = NULL; - *fmask_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_FMASK); + *fmask_ptr = get_sampler_desc(ctx, ind_index, DESC_FMASK); } else { - *samp_ptr = get_sampler_desc(si_shader_ctx, ind_index, DESC_SAMPLER); + *samp_ptr = get_sampler_desc(ctx, ind_index, DESC_SAMPLER); *fmask_ptr = NULL; } } else { - *res_ptr = si_shader_ctx->sampler_views[sampler_index]; - *samp_ptr = si_shader_ctx->sampler_states[sampler_index]; - *fmask_ptr = si_shader_ctx->fmasks[sampler_index]; + *res_ptr = ctx->sampler_views[sampler_index]; + *samp_ptr = ctx->sampler_states[sampler_index]; + *fmask_ptr = ctx->fmasks[sampler_index]; } } static void tex_fetch_args( - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) + struct lp_build_tgsi_context *bld_base, + struct lp_build_emit_data *emit_data) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMBuilderRef builder = gallivm->builder; - const struct tgsi_full_instruction * inst = emit_data->inst; + const struct tgsi_full_instruction *inst = emit_data->inst; unsigned opcode = inst->Instruction.Opcode; unsigned target = inst->Texture.Texture; LLVMValueRef coords[5], derivs[6]; @@ -2625,21 +2622,18 @@ static void tex_fetch_args( unsigned num_deriv_channels = 0; bool has_offset = inst->Texture.NumOffsets > 0; LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); unsigned dmask = 0xf; tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr); if (opcode == TGSI_OPCODE_TXQ) { if (target == TGSI_TEXTURE_BUFFER) { - LLVMTypeRef v8i32 = LLVMVectorType(i32, 8); - /* Read the size from the buffer descriptor directly. */ - LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, ""); + LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, ""); LLVMValueRef size = LLVMBuildExtractElement(builder, res, lp_build_const_int32(gallivm, 6), ""); - if (si_shader_ctx->screen->b.chip_class >= VI) { + if (ctx->screen->b.chip_class >= VI) { /* On VI, the descriptor contains the size in bytes, * but TXQ must return the size in elements. * The stride is always non-zero for resources using TXQ. @@ -2662,24 +2656,21 @@ static void tex_fetch_args( /* Textures - set the mip level. */ address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X); - set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr, + set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr, NULL, address, count, 0xf); return; } if (target == TGSI_TEXTURE_BUFFER) { - LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128); - LLVMTypeRef v2i128 = LLVMVectorType(i128, 2); - LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context); - LLVMTypeRef v16i8 = LLVMVectorType(i8, 16); + LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2); /* Bitcast and truncate v8i32 to v16i8. */ LLVMValueRef res = res_ptr; res = LLVMBuildBitCast(gallivm->builder, res, v2i128, ""); res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, ""); - res = LLVMBuildBitCast(gallivm->builder, res, v16i8, ""); + res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, ""); - emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4); + emit_data->dst_type = ctx->v4f32; emit_data->args[0] = res; emit_data->args[1] = bld_base->uint_bld.zero; emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X); @@ -2816,7 +2807,7 @@ static void tex_fetch_args( for (chan = 0; chan < count; chan++ ) { address[chan] = LLVMBuildBitCast(gallivm->builder, - address[chan], i32, ""); + address[chan], ctx->i32, ""); } /* Adjust the sample index according to FMASK. @@ -2853,14 +2844,14 @@ static void tex_fetch_args( inst.Texture.Texture = target; txf_emit_data.inst = &inst; txf_emit_data.chan = 0; - set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF, + set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF, target, fmask_ptr, NULL, txf_address, txf_count, 0xf); build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data); /* Initialize some constants. */ - LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0); - LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0); + LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0); + LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0); /* Apply the formula. */ LLVMValueRef fmask = @@ -2884,7 +2875,7 @@ static void tex_fetch_args( */ LLVMValueRef fmask_desc = LLVMBuildBitCast(gallivm->builder, fmask_ptr, - LLVMVectorType(uint_bld->elem_type, 8), ""); + ctx->v8i32, ""); LLVMValueRef fmask_word1 = LLVMBuildExtractElement(gallivm->builder, fmask_desc, @@ -2905,7 +2896,7 @@ static void tex_fetch_args( if (inst->Texture.NumOffsets) { struct lp_build_context *uint_bld = &bld_base->uint_bld; struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base); - const struct tgsi_texture_offset * off = inst->TexOffsets; + const struct tgsi_texture_offset *off = inst->TexOffsets; assert(inst->Texture.NumOffsets == 1); @@ -2964,15 +2955,15 @@ static void tex_fetch_args( dmask = 1 << gather_comp; } - set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr, + set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr, samp_ptr, address, count, dmask); } -static void build_tex_intrinsic(const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) +static void build_tex_intrinsic(const struct lp_build_tgsi_action *action, + struct lp_build_tgsi_context *bld_base, + struct lp_build_emit_data *emit_data) { - struct lp_build_context * base = &bld_base->base; + struct lp_build_context *base = &bld_base->base; unsigned opcode = emit_data->inst->Instruction.Opcode; unsigned target = emit_data->inst->Texture.Texture; char intr_name[127]; @@ -3073,14 +3064,13 @@ static void build_tex_intrinsic(const struct lp_build_tgsi_action * action, } static void si_llvm_emit_txqs( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) + const struct lp_build_tgsi_action *action, + struct lp_build_tgsi_context *bld_base, + struct lp_build_emit_data *emit_data) { + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMBuilderRef builder = gallivm->builder; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); - LLVMTypeRef v8i32 = LLVMVectorType(i32, 8); LLVMValueRef res, samples; LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL; @@ -3088,7 +3078,7 @@ static void si_llvm_emit_txqs( /* Read the samples from the descriptor directly. */ - res = LLVMBuildBitCast(builder, res_ptr, v8i32, ""); + res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, ""); samples = LLVMBuildExtractElement( builder, res, lp_build_const_int32(gallivm, 3), ""); @@ -3132,30 +3122,26 @@ static void si_llvm_emit_txqs( #define TID_MASK_LEFT 0xfffffffe static void si_llvm_emit_ddxy( - const struct lp_build_tgsi_action * action, - struct lp_build_tgsi_context * bld_base, - struct lp_build_emit_data * emit_data) + const struct lp_build_tgsi_action *action, + struct lp_build_tgsi_context *bld_base, + struct lp_build_emit_data *emit_data) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; - struct lp_build_context * base = &bld_base->base; const struct tgsi_full_instruction *inst = emit_data->inst; unsigned opcode = inst->Instruction.Opcode; LLVMValueRef indices[2]; LLVMValueRef store_ptr, load_ptr0, load_ptr1; LLVMValueRef tl, trbl, result[4]; - LLVMTypeRef i32; unsigned swizzle[4]; unsigned c; int idx; unsigned mask; - i32 = LLVMInt32TypeInContext(gallivm->context); - indices[0] = bld_base->uint_bld.zero; - indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32, + indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32, NULL, 0, LLVMReadNoneAttribute); - store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); if (opcode == TGSI_OPCODE_DDX_FINE) @@ -3167,14 +3153,14 @@ static void si_llvm_emit_ddxy( indices[1] = LLVMBuildAnd(gallivm->builder, indices[1], lp_build_const_int32(gallivm, mask), ""); - load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + load_ptr0 = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); /* for DDX we want to next X pixel, DDY next Y pixel. */ idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2; indices[1] = LLVMBuildAdd(gallivm->builder, indices[1], lp_build_const_int32(gallivm, idx), ""); - load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + load_ptr1 = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); for (c = 0; c < 4; ++c) { @@ -3193,14 +3179,14 @@ static void si_llvm_emit_ddxy( LLVMBuildStore(gallivm->builder, LLVMBuildBitCast(gallivm->builder, lp_build_emit_fetch(bld_base, inst, 0, c), - i32, ""), + ctx->i32, ""), store_ptr); tl = LLVMBuildLoad(gallivm->builder, load_ptr0, ""); - tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, ""); + tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, ""); trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, ""); - trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, ""); + trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, ""); result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, ""); } @@ -3217,21 +3203,17 @@ static LLVMValueRef si_llvm_emit_ddxy_interp( struct lp_build_tgsi_context *bld_base, LLVMValueRef interp_ij) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; - struct lp_build_context *base = &bld_base->base; LLVMValueRef indices[2]; LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2; LLVMValueRef tl, tr, bl, result[4]; - LLVMTypeRef i32; unsigned c; - i32 = LLVMInt32TypeInContext(gallivm->context); - indices[0] = bld_base->uint_bld.zero; - indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32, + indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", ctx->i32, NULL, 0, LLVMReadNoneAttribute); - store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + store_ptr = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); temp = LLVMBuildAnd(gallivm->builder, indices[1], @@ -3241,21 +3223,21 @@ static LLVMValueRef si_llvm_emit_ddxy_interp( lp_build_const_int32(gallivm, TID_MASK_TOP), ""); indices[1] = temp; - load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + load_ptr_x = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); indices[1] = temp2; - load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + load_ptr_y = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); indices[1] = LLVMBuildAdd(gallivm->builder, temp, lp_build_const_int32(gallivm, 1), ""); - load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + load_ptr_ddx = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); indices[1] = LLVMBuildAdd(gallivm->builder, temp2, lp_build_const_int32(gallivm, 2), ""); - load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds, + load_ptr_ddy = LLVMBuildGEP(gallivm->builder, ctx->lds, indices, 2, ""); for (c = 0; c < 2; ++c) { @@ -3269,18 +3251,18 @@ static LLVMValueRef si_llvm_emit_ddxy_interp( store_ptr); tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, ""); - tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, ""); + tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, ""); tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, ""); - tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, ""); + tr = LLVMBuildBitCast(gallivm->builder, tr, ctx->f32, ""); result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, ""); tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, ""); - tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, ""); + tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, ""); bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, ""); - bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, ""); + bl = LLVMBuildBitCast(gallivm->builder, bl, ctx->f32, ""); result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, ""); } @@ -3292,7 +3274,7 @@ static void interp_fetch_args( struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; const struct tgsi_full_instruction *inst = emit_data->inst; @@ -3316,9 +3298,8 @@ static void interp_fetch_args( sample_id = lp_build_emit_fetch(bld_base, emit_data->inst, 1, TGSI_CHAN_X); sample_id = LLVMBuildBitCast(gallivm->builder, sample_id, - LLVMInt32TypeInContext(gallivm->context), - ""); - sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id); + ctx->i32, ""); + sample_position = load_sample_position(&ctx->radeon_bld, sample_id); emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder, sample_position, @@ -3337,8 +3318,8 @@ static void build_interp_intrinsic(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); - struct si_shader *shader = si_shader_ctx->shader; + struct si_shader_context *ctx = si_shader_context(bld_base); + struct si_shader *shader = ctx->shader; struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef interp_param; const struct tgsi_full_instruction *inst = emit_data->inst; @@ -3347,8 +3328,7 @@ static void build_interp_intrinsic(const struct lp_build_tgsi_action *action, int chan; int i; LLVMValueRef attr_number; - LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context); - LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK); + LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK); int interp_param_idx; unsigned interp = shader->selector->info.input_interpolate[input_index]; unsigned location; @@ -3365,7 +3345,7 @@ static void build_interp_intrinsic(const struct lp_build_tgsi_action *action, if (interp_param_idx == -1) return; else if (interp_param_idx) - interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx); + interp_param = LLVMGetParam(ctx->radeon_bld.main_fn, interp_param_idx); else interp_param = NULL; @@ -3396,7 +3376,7 @@ static void build_interp_intrinsic(const struct lp_build_tgsi_action *action, LLVMValueRef temp1, temp2; interp_el = LLVMBuildBitCast(gallivm->builder, interp_el, - LLVMFloatTypeInContext(gallivm->context), ""); + ctx->f32, ""); temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], ""); @@ -3407,8 +3387,7 @@ static void build_interp_intrinsic(const struct lp_build_tgsi_action *action, temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, ""); ij_out[i] = LLVMBuildBitCast(gallivm->builder, - temp2, - LLVMIntTypeInContext(gallivm->context, 32), ""); + temp2, ctx->i32, ""); } interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2); } @@ -3429,7 +3408,7 @@ static void build_interp_intrinsic(const struct lp_build_tgsi_action *action, emit_data->output[chan] = lp_build_intrinsic(gallivm->builder, intr_name, - input_type, args, args[3] ? 4 : 3, + ctx->f32, args, args[3] ? 4 : 3, LLVMReadNoneAttribute | LLVMNoUnwindAttribute); } } @@ -3453,13 +3432,12 @@ static void si_llvm_emit_vertex( struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct lp_build_context *uint = &bld_base->uint_bld; - struct si_shader *shader = si_shader_ctx->shader; + struct si_shader *shader = ctx->shader; struct tgsi_shader_info *info = &shader->selector->info; struct gallivm_state *gallivm = bld_base->base.gallivm; - LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context); - LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS2VS_OFFSET); LLVMValueRef gs_next_vertex; LLVMValueRef can_emit, kill; @@ -3472,7 +3450,7 @@ static void si_llvm_emit_vertex( /* Write vertex attribute values to GSVS ring */ gs_next_vertex = LLVMBuildLoad(gallivm->builder, - si_shader_ctx->gs_next_vertex[stream], + ctx->gs_next_vertex[stream], ""); /* If this thread has already emitted the declared maximum number of @@ -3488,11 +3466,11 @@ static void si_llvm_emit_vertex( lp_build_const_float(gallivm, -1.0f)); lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill", - LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0); + ctx->voidt, &kill, 1, 0); for (i = 0; i < info->num_outputs; i++) { LLVMValueRef *out_ptr = - si_shader_ctx->radeon_bld.soa.outputs[i]; + ctx->radeon_bld.soa.outputs[i]; for (chan = 0; chan < 4; chan++) { LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""); @@ -3503,10 +3481,10 @@ static void si_llvm_emit_vertex( voffset = lp_build_add(uint, voffset, gs_next_vertex); voffset = lp_build_mul_imm(uint, voffset, 4); - out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, ""); + out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, ""); - build_tbuffer_store(si_shader_ctx, - si_shader_ctx->gsvs_ring[stream], + build_tbuffer_store(ctx, + ctx->gsvs_ring[stream], out_val, 1, voffset, soffset, 0, V_008F0C_BUF_DATA_FORMAT_32, @@ -3517,14 +3495,13 @@ static void si_llvm_emit_vertex( gs_next_vertex = lp_build_add(uint, gs_next_vertex, lp_build_const_int32(gallivm, 1)); - LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]); + LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]); /* Signal vertex emission */ args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8)); - args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); + args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg", - LLVMVoidTypeInContext(gallivm->context), args, 2, - LLVMNoUnwindAttribute); + ctx->voidt, args, 2, LLVMNoUnwindAttribute); } /* Cut one primitive from the geometry shader */ @@ -3533,7 +3510,7 @@ static void si_llvm_emit_primitive( struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { - struct si_shader_context *si_shader_ctx = si_shader_context(bld_base); + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; LLVMValueRef args[2]; unsigned stream; @@ -3541,23 +3518,22 @@ static void si_llvm_emit_primitive( /* Signal primitive cut */ stream = si_llvm_get_stream(bld_base, emit_data); args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8)); - args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); + args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID); lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg", - LLVMVoidTypeInContext(gallivm->context), args, 2, - LLVMNoUnwindAttribute); + ctx->voidt, args, 2, LLVMNoUnwindAttribute); } static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action, struct lp_build_tgsi_context *bld_base, struct lp_build_emit_data *emit_data) { + struct si_shader_context *ctx = si_shader_context(bld_base); struct gallivm_state *gallivm = bld_base->base.gallivm; lp_build_intrinsic(gallivm->builder, - HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier" - : "llvm.AMDGPU.barrier.local", - LLVMVoidTypeInContext(gallivm->context), NULL, 0, - LLVMNoUnwindAttribute); + HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier" + : "llvm.AMDGPU.barrier.local", + ctx->voidt, NULL, 0, LLVMNoUnwindAttribute); } static const struct lp_build_tgsi_action tex_action = { @@ -3570,19 +3546,19 @@ static const struct lp_build_tgsi_action interp_action = { .emit = build_interp_intrinsic, }; -static void create_meta_data(struct si_shader_context *si_shader_ctx) +static void create_meta_data(struct si_shader_context *ctx) { - struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm; + struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm; LLVMValueRef args[3]; args[0] = LLVMMDStringInContext(gallivm->context, "const", 5); args[1] = 0; args[2] = lp_build_const_int32(gallivm, 1); - si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3); + ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3); } -static void declare_streamout_params(struct si_shader_context *si_shader_ctx, +static void declare_streamout_params(struct si_shader_context *ctx, struct pipe_stream_output_info *so, LLVMTypeRef *params, LLVMTypeRef i32, unsigned *num_params) @@ -3591,129 +3567,124 @@ static void declare_streamout_params(struct si_shader_context *si_shader_ctx, /* Streamout SGPRs. */ if (so->num_outputs) { - params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32; - params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32; + params[ctx->param_streamout_config = (*num_params)++] = i32; + params[ctx->param_streamout_write_index = (*num_params)++] = i32; } /* A streamout buffer offset is loaded if the stride is non-zero. */ for (i = 0; i < 4; i++) { if (!so->stride[i]) continue; - params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32; + params[ctx->param_streamout_offset[i] = (*num_params)++] = i32; } } -static void create_function(struct si_shader_context *si_shader_ctx) +static void create_function(struct si_shader_context *ctx) { - struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base; + struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; struct gallivm_state *gallivm = bld_base->base.gallivm; - struct si_shader *shader = si_shader_ctx->shader; - LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v8i32; + struct si_shader *shader = ctx->shader; + LLVMTypeRef params[SI_NUM_PARAMS], v2i32, v3i32; unsigned i, last_array_pointer, last_sgpr, num_params; - i8 = LLVMInt8TypeInContext(gallivm->context); - i32 = LLVMInt32TypeInContext(gallivm->context); - f32 = LLVMFloatTypeInContext(gallivm->context); - v2i32 = LLVMVectorType(i32, 2); - v3i32 = LLVMVectorType(i32, 3); - v8i32 = LLVMVectorType(i32, 8); - v16i8 = LLVMVectorType(i8, 16); - - params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS); - params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS); - params[SI_PARAM_SAMPLERS] = const_array(v8i32, SI_NUM_SAMPLERS); - params[SI_PARAM_UNUSED] = LLVMPointerType(i32, CONST_ADDR_SPACE); + v2i32 = LLVMVectorType(ctx->i32, 2); + v3i32 = LLVMVectorType(ctx->i32, 3); + + params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS); + params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS); + params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS); + params[SI_PARAM_UNUSED] = LLVMPointerType(ctx->i32, CONST_ADDR_SPACE); last_array_pointer = SI_PARAM_UNUSED; - switch (si_shader_ctx->type) { + switch (ctx->type) { case TGSI_PROCESSOR_VERTEX: - params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS); + params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS); last_array_pointer = SI_PARAM_VERTEX_BUFFERS; - params[SI_PARAM_BASE_VERTEX] = i32; - params[SI_PARAM_START_INSTANCE] = i32; + params[SI_PARAM_BASE_VERTEX] = ctx->i32; + params[SI_PARAM_START_INSTANCE] = ctx->i32; num_params = SI_PARAM_START_INSTANCE+1; if (shader->key.vs.as_es) { - params[si_shader_ctx->param_es2gs_offset = num_params++] = i32; + params[ctx->param_es2gs_offset = num_params++] = ctx->i32; } else if (shader->key.vs.as_ls) { - params[SI_PARAM_LS_OUT_LAYOUT] = i32; + params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32; num_params = SI_PARAM_LS_OUT_LAYOUT+1; } else { - if (si_shader_ctx->is_gs_copy_shader) { + if (ctx->is_gs_copy_shader) { last_array_pointer = SI_PARAM_CONST_BUFFERS; num_params = SI_PARAM_CONST_BUFFERS+1; } else { - params[SI_PARAM_VS_STATE_BITS] = i32; + params[SI_PARAM_VS_STATE_BITS] = ctx->i32; num_params = SI_PARAM_VS_STATE_BITS+1; } /* The locations of the other parameters are assigned dynamically. */ - declare_streamout_params(si_shader_ctx, &shader->selector->so, - params, i32, &num_params); + declare_streamout_params(ctx, &shader->selector->so, + params, ctx->i32, &num_params); } last_sgpr = num_params-1; /* VGPRs */ - params[si_shader_ctx->param_vertex_id = num_params++] = i32; - params[si_shader_ctx->param_rel_auto_id = num_params++] = i32; - params[si_shader_ctx->param_vs_prim_id = num_params++] = i32; - params[si_shader_ctx->param_instance_id = num_params++] = i32; + params[ctx->param_vertex_id = num_params++] = ctx->i32; + params[ctx->param_rel_auto_id = num_params++] = ctx->i32; + params[ctx->param_vs_prim_id = num_params++] = ctx->i32; + params[ctx->param_instance_id = num_params++] = ctx->i32; break; case TGSI_PROCESSOR_TESS_CTRL: - params[SI_PARAM_TCS_OUT_OFFSETS] = i32; - params[SI_PARAM_TCS_OUT_LAYOUT] = i32; - params[SI_PARAM_TCS_IN_LAYOUT] = i32; - params[SI_PARAM_TESS_FACTOR_OFFSET] = i32; + params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32; + params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32; + params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32; + params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32; last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET; /* VGPRs */ - params[SI_PARAM_PATCH_ID] = i32; - params[SI_PARAM_REL_IDS] = i32; + params[SI_PARAM_PATCH_ID] = ctx->i32; + params[SI_PARAM_REL_IDS] = ctx->i32; num_params = SI_PARAM_REL_IDS+1; break; case TGSI_PROCESSOR_TESS_EVAL: - params[SI_PARAM_TCS_OUT_OFFSETS] = i32; - params[SI_PARAM_TCS_OUT_LAYOUT] = i32; + params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32; + params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32; num_params = SI_PARAM_TCS_OUT_LAYOUT+1; if (shader->key.tes.as_es) { - params[si_shader_ctx->param_es2gs_offset = num_params++] = i32; + params[ctx->param_es2gs_offset = num_params++] = ctx->i32; } else { - declare_streamout_params(si_shader_ctx, &shader->selector->so, - params, i32, &num_params); + declare_streamout_params(ctx, &shader->selector->so, + params, ctx->i32, &num_params); } last_sgpr = num_params - 1; /* VGPRs */ - params[si_shader_ctx->param_tes_u = num_params++] = f32; - params[si_shader_ctx->param_tes_v = num_params++] = f32; - params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32; - params[si_shader_ctx->param_tes_patch_id = num_params++] = i32; + params[ctx->param_tes_u = num_params++] = ctx->f32; + params[ctx->param_tes_v = num_params++] = ctx->f32; + params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32; + params[ctx->param_tes_patch_id = num_params++] = ctx->i32; break; case TGSI_PROCESSOR_GEOMETRY: - params[SI_PARAM_GS2VS_OFFSET] = i32; - params[SI_PARAM_GS_WAVE_ID] = i32; + params[SI_PARAM_GS2VS_OFFSET] = ctx->i32; + params[SI_PARAM_GS_WAVE_ID] = ctx->i32; last_sgpr = SI_PARAM_GS_WAVE_ID; /* VGPRs */ - params[SI_PARAM_VTX0_OFFSET] = i32; - params[SI_PARAM_VTX1_OFFSET] = i32; - params[SI_PARAM_PRIMITIVE_ID] = i32; - params[SI_PARAM_VTX2_OFFSET] = i32; - params[SI_PARAM_VTX3_OFFSET] = i32; - params[SI_PARAM_VTX4_OFFSET] = i32; - params[SI_PARAM_VTX5_OFFSET] = i32; - params[SI_PARAM_GS_INSTANCE_ID] = i32; + params[SI_PARAM_VTX0_OFFSET] = ctx->i32; + params[SI_PARAM_VTX1_OFFSET] = ctx->i32; + params[SI_PARAM_PRIMITIVE_ID] = ctx->i32; + params[SI_PARAM_VTX2_OFFSET] = ctx->i32; + params[SI_PARAM_VTX3_OFFSET] = ctx->i32; + params[SI_PARAM_VTX4_OFFSET] = ctx->i32; + params[SI_PARAM_VTX5_OFFSET] = ctx->i32; + params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32; num_params = SI_PARAM_GS_INSTANCE_ID+1; break; case TGSI_PROCESSOR_FRAGMENT: - params[SI_PARAM_ALPHA_REF] = f32; - params[SI_PARAM_PRIM_MASK] = i32; + params[SI_PARAM_ALPHA_REF] = ctx->f32; + params[SI_PARAM_PRIM_MASK] = ctx->i32; last_sgpr = SI_PARAM_PRIM_MASK; params[SI_PARAM_PERSP_SAMPLE] = v2i32; params[SI_PARAM_PERSP_CENTER] = v2i32; @@ -3722,15 +3693,15 @@ static void create_function(struct si_shader_context *si_shader_ctx) params[SI_PARAM_LINEAR_SAMPLE] = v2i32; params[SI_PARAM_LINEAR_CENTER] = v2i32; params[SI_PARAM_LINEAR_CENTROID] = v2i32; - params[SI_PARAM_LINE_STIPPLE_TEX] = f32; - params[SI_PARAM_POS_X_FLOAT] = f32; - params[SI_PARAM_POS_Y_FLOAT] = f32; - params[SI_PARAM_POS_Z_FLOAT] = f32; - params[SI_PARAM_POS_W_FLOAT] = f32; - params[SI_PARAM_FRONT_FACE] = i32; - params[SI_PARAM_ANCILLARY] = i32; - params[SI_PARAM_SAMPLE_COVERAGE] = f32; - params[SI_PARAM_POS_FIXED_PT] = f32; + params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32; + params[SI_PARAM_POS_X_FLOAT] = ctx->f32; + params[SI_PARAM_POS_Y_FLOAT] = ctx->f32; + params[SI_PARAM_POS_Z_FLOAT] = ctx->f32; + params[SI_PARAM_POS_W_FLOAT] = ctx->f32; + params[SI_PARAM_FRONT_FACE] = ctx->i32; + params[SI_PARAM_ANCILLARY] = ctx->i32; + params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32; + params[SI_PARAM_POS_FIXED_PT] = ctx->f32; num_params = SI_PARAM_POS_FIXED_PT+1; break; @@ -3740,11 +3711,11 @@ static void create_function(struct si_shader_context *si_shader_ctx) } assert(num_params <= Elements(params)); - radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params); - radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type); + radeon_llvm_create_func(&ctx->radeon_bld, params, num_params); + radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type); for (i = 0; i <= last_sgpr; ++i) { - LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i); + LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i); /* We tell llvm that array inputs are passed by value to allow Sinking pass * to move load. Inputs are constant so this is fine. */ @@ -3761,15 +3732,15 @@ static void create_function(struct si_shader_context *si_shader_ctx) bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 || bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 || bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0)) - si_shader_ctx->lds = + ctx->lds = LLVMAddGlobalInAddressSpace(gallivm->module, - LLVMArrayType(i32, 64), + LLVMArrayType(ctx->i32, 64), "ddxy_lds", LOCAL_ADDR_SPACE); - if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) || - si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL || - si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) { + if ((ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) || + ctx->type == TGSI_PROCESSOR_TESS_CTRL || + ctx->type == TGSI_PROCESSOR_TESS_EVAL) { /* This is the upper bound, maximum is 32 inputs times 32 vertices */ unsigned vertex_data_dw_size = 32*32*4; unsigned patch_data_dw_size = 32*4; @@ -3779,21 +3750,21 @@ static void create_function(struct si_shader_context *si_shader_ctx) /* The actual size is computed outside of the shader to reduce * the number of shader variants. */ - si_shader_ctx->lds = + ctx->lds = LLVMAddGlobalInAddressSpace(gallivm->module, - LLVMArrayType(i32, lds_dwords), + LLVMArrayType(ctx->i32, lds_dwords), "tess_lds", LOCAL_ADDR_SPACE); } } -static void preload_constants(struct si_shader_context *si_shader_ctx) +static void preload_constants(struct si_shader_context *ctx) { - struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base; - struct gallivm_state * gallivm = bld_base->base.gallivm; - const struct tgsi_shader_info * info = bld_base->info; + struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = bld_base->base.gallivm; + const struct tgsi_shader_info *info = bld_base->info; unsigned buf; - LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); + LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS); for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) { unsigned i, num_const = info->const_file_max[buf] + 1; @@ -3802,28 +3773,28 @@ static void preload_constants(struct si_shader_context *si_shader_ctx) continue; /* Allocate space for the constant values */ - si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef)); + ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef)); /* Load the resource descriptor */ - si_shader_ctx->const_buffers[buf] = - build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf)); + ctx->const_buffers[buf] = + build_indexed_load_const(ctx, ptr, lp_build_const_int32(gallivm, buf)); /* Load the constants, we rely on the code sinking to do the rest */ for (i = 0; i < num_const * 4; ++i) { - si_shader_ctx->constants[buf][i] = + ctx->constants[buf][i] = buffer_load_const(gallivm->builder, - si_shader_ctx->const_buffers[buf], + ctx->const_buffers[buf], lp_build_const_int32(gallivm, i * 4), - bld_base->base.elem_type); + ctx->f32); } } } -static void preload_samplers(struct si_shader_context *si_shader_ctx) +static void preload_samplers(struct si_shader_context *ctx) { - struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base; - struct gallivm_state * gallivm = bld_base->base.gallivm; - const struct tgsi_shader_info * info = bld_base->info; + struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = bld_base->base.gallivm; + const struct tgsi_shader_info *info = bld_base->info; unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1; LLVMValueRef offset; @@ -3834,44 +3805,44 @@ static void preload_samplers(struct si_shader_context *si_shader_ctx) for (i = 0; i < num_samplers; ++i) { /* Resource */ offset = lp_build_const_int32(gallivm, i); - si_shader_ctx->sampler_views[i] = - get_sampler_desc(si_shader_ctx, offset, DESC_IMAGE); + ctx->sampler_views[i] = + get_sampler_desc(ctx, offset, DESC_IMAGE); /* FMASK resource */ if (info->is_msaa_sampler[i]) - si_shader_ctx->fmasks[i] = - get_sampler_desc(si_shader_ctx, offset, DESC_FMASK); + ctx->fmasks[i] = + get_sampler_desc(ctx, offset, DESC_FMASK); else - si_shader_ctx->sampler_states[i] = - get_sampler_desc(si_shader_ctx, offset, DESC_SAMPLER); + ctx->sampler_states[i] = + get_sampler_desc(ctx, offset, DESC_SAMPLER); } } -static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx) +static void preload_streamout_buffers(struct si_shader_context *ctx) { - struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base; - struct gallivm_state * gallivm = bld_base->base.gallivm; + struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; + struct gallivm_state *gallivm = bld_base->base.gallivm; unsigned i; /* Streamout can only be used if the shader is compiled as VS. */ - if (!si_shader_ctx->shader->selector->so.num_outputs || - (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && - (si_shader_ctx->shader->key.vs.as_es || - si_shader_ctx->shader->key.vs.as_ls)) || - (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL && - si_shader_ctx->shader->key.tes.as_es)) + if (!ctx->shader->selector->so.num_outputs || + (ctx->type == TGSI_PROCESSOR_VERTEX && + (ctx->shader->key.vs.as_es || + ctx->shader->key.vs.as_ls)) || + (ctx->type == TGSI_PROCESSOR_TESS_EVAL && + ctx->shader->key.tes.as_es)) return; - LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); /* Load the resources, we rely on the code sinking to do the rest */ for (i = 0; i < 4; ++i) { - if (si_shader_ctx->shader->selector->so.stride[i]) { + if (ctx->shader->selector->so.stride[i]) { LLVMValueRef offset = lp_build_const_int32(gallivm, SI_SO_BUF_OFFSET + i); - si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset); + ctx->so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset); } } } @@ -3880,38 +3851,38 @@ static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx) * Load ESGS and GSVS ring buffer resource descriptors and save the variables * for later use. */ -static void preload_ring_buffers(struct si_shader_context *si_shader_ctx) +static void preload_ring_buffers(struct si_shader_context *ctx) { struct gallivm_state *gallivm = - si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm; + ctx->radeon_bld.soa.bld_base.base.gallivm; - LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, + LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS); - if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && - si_shader_ctx->shader->key.vs.as_es) || - (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL && - si_shader_ctx->shader->key.tes.as_es) || - si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) { + if ((ctx->type == TGSI_PROCESSOR_VERTEX && + ctx->shader->key.vs.as_es) || + (ctx->type == TGSI_PROCESSOR_TESS_EVAL && + ctx->shader->key.tes.as_es) || + ctx->type == TGSI_PROCESSOR_GEOMETRY) { LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS); - si_shader_ctx->esgs_ring = - build_indexed_load_const(si_shader_ctx, buf_ptr, offset); + ctx->esgs_ring = + build_indexed_load_const(ctx, buf_ptr, offset); } - if (si_shader_ctx->is_gs_copy_shader) { + if (ctx->is_gs_copy_shader) { LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS); - si_shader_ctx->gsvs_ring[0] = - build_indexed_load_const(si_shader_ctx, buf_ptr, offset); + ctx->gsvs_ring[0] = + build_indexed_load_const(ctx, buf_ptr, offset); } - if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx->type == TGSI_PROCESSOR_GEOMETRY) { int i; for (i = 0; i < 4; i++) { LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i); - si_shader_ctx->gsvs_ring[i] = - build_indexed_load_const(si_shader_ctx, buf_ptr, offset); + ctx->gsvs_ring[i] = + build_indexed_load_const(ctx, buf_ptr, offset); } } } @@ -4211,13 +4182,12 @@ int si_compile_llvm(struct si_screen *sscreen, /* Generate code for the hardware VS shader stage to go with a geometry shader */ static int si_generate_gs_copy_shader(struct si_screen *sscreen, - struct si_shader_context *si_shader_ctx, + struct si_shader_context *ctx, struct si_shader *gs, struct pipe_debug_callback *debug) { - struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm; - struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base; - struct lp_build_context *base = &bld_base->base; + struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm; + struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base; struct lp_build_context *uint = &bld_base->uint_bld; struct si_shader_output_values *outputs; struct tgsi_shader_info *gsinfo = &gs->selector->info; @@ -4226,20 +4196,19 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0])); - si_shader_ctx->type = TGSI_PROCESSOR_VERTEX; - si_shader_ctx->is_gs_copy_shader = true; - - radeon_llvm_context_init(&si_shader_ctx->radeon_bld); + si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm, gsinfo); + ctx->type = TGSI_PROCESSOR_VERTEX; + ctx->is_gs_copy_shader = true; - create_meta_data(si_shader_ctx); - create_function(si_shader_ctx); - preload_streamout_buffers(si_shader_ctx); - preload_ring_buffers(si_shader_ctx); + create_meta_data(ctx); + create_function(ctx); + preload_streamout_buffers(ctx); + preload_ring_buffers(ctx); - args[0] = si_shader_ctx->gsvs_ring[0]; + args[0] = ctx->gsvs_ring[0]; args[1] = lp_build_mul_imm(uint, - LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, - si_shader_ctx->param_vertex_id), + LLVMGetParam(ctx->radeon_bld.main_fn, + ctx->param_vertex_id), 4); args[3] = uint->zero; args[4] = uint->one; /* OFFEN */ @@ -4264,10 +4233,9 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, LLVMBuildBitCast(gallivm->builder, lp_build_intrinsic(gallivm->builder, "llvm.SI.buffer.load.dword.i32.i32", - LLVMInt32TypeInContext(gallivm->context), - args, 9, + ctx->i32, args, 9, LLVMReadOnlyAttribute | LLVMNoUnwindAttribute), - base->elem_type, ""); + ctx->f32, ""); } } @@ -4280,22 +4248,22 @@ static int si_generate_gs_copy_shader(struct si_screen *sscreen, r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY)) LLVMDumpModule(bld_base->base.gallivm->module); - radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld); + radeon_llvm_finalize_module(&ctx->radeon_bld); - r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary, - &si_shader_ctx->shader->config, si_shader_ctx->tm, + r = si_compile_llvm(sscreen, &ctx->shader->binary, + &ctx->shader->config, ctx->tm, bld_base->base.gallivm->module, debug, TGSI_PROCESSOR_GEOMETRY, "GS Copy Shader"); if (!r) { if (r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY)) fprintf(stderr, "GS Copy Shader:\n"); - si_shader_dump(sscreen, si_shader_ctx->shader, debug, + si_shader_dump(sscreen, ctx->shader, debug, TGSI_PROCESSOR_GEOMETRY); - r = si_shader_binary_upload(sscreen, si_shader_ctx->shader); + r = si_shader_binary_upload(sscreen, ctx->shader); } - radeon_llvm_dispose(&si_shader_ctx->radeon_bld); + radeon_llvm_dispose(&ctx->radeon_bld); FREE(outputs); return r; @@ -4364,6 +4332,17 @@ static void si_init_shader_ctx(struct si_shader_context *ctx, ctx->type = -1; ctx->shader = shader; + ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context); + ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context); + ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context); + ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context); + ctx->i128 = LLVMInt128TypeInContext(ctx->radeon_bld.gallivm.context); + ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context); + ctx->v16i8 = LLVMVectorType(ctx->i8, 16); + ctx->v4i32 = LLVMVectorType(ctx->i32, 4); + ctx->v4f32 = LLVMVectorType(ctx->f32, 4); + ctx->v8i32 = LLVMVectorType(ctx->i32, 8); + bld_base = &ctx->radeon_bld.soa.bld_base; bld_base->info = info; bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant; @@ -4395,12 +4374,10 @@ static void si_init_shader_ctx(struct si_shader_context *ctx, bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive; bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier; - if (HAVE_LLVM >= 0x0306) { - bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32"; - bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem; - bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32"; - } + bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem; + bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32"; + bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem; + bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32"; } int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, @@ -4409,8 +4386,8 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, { struct si_shader_selector *sel = shader->selector; struct tgsi_token *tokens = sel->tokens; - struct si_shader_context si_shader_ctx; - struct lp_build_tgsi_context * bld_base; + struct si_shader_context ctx; + struct lp_build_tgsi_context *bld_base; struct tgsi_shader_info stipple_shader_info; LLVMModuleRef mod; int r = 0; @@ -4433,17 +4410,17 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, si_dump_streamout(&sel->so); } - si_init_shader_ctx(&si_shader_ctx, sscreen, shader, tm, + si_init_shader_ctx(&ctx, sscreen, shader, tm, poly_stipple ? &stipple_shader_info : &sel->info); shader->uses_instanceid = sel->info.uses_instanceid; - bld_base = &si_shader_ctx.radeon_bld.soa.bld_base; - si_shader_ctx.radeon_bld.load_system_value = declare_system_value; + bld_base = &ctx.radeon_bld.soa.bld_base; + ctx.radeon_bld.load_system_value = declare_system_value; - switch (si_shader_ctx.type) { + switch (ctx.type) { case TGSI_PROCESSOR_VERTEX: - si_shader_ctx.radeon_bld.load_input = declare_input_vs; + ctx.radeon_bld.load_input = declare_input_vs; if (shader->key.vs.as_ls) bld_base->emit_epilogue = si_llvm_emit_ls_epilogue; else if (shader->key.vs.as_es) @@ -4469,7 +4446,7 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, bld_base->emit_epilogue = si_llvm_emit_gs_epilogue; break; case TGSI_PROCESSOR_FRAGMENT: - si_shader_ctx.radeon_bld.load_input = declare_input_fs; + ctx.radeon_bld.load_input = declare_input_fs; bld_base->emit_epilogue = si_llvm_emit_fs_epilogue; break; default: @@ -4477,19 +4454,19 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, return -1; } - create_meta_data(&si_shader_ctx); - create_function(&si_shader_ctx); - preload_constants(&si_shader_ctx); - preload_samplers(&si_shader_ctx); - preload_streamout_buffers(&si_shader_ctx); - preload_ring_buffers(&si_shader_ctx); + create_meta_data(&ctx); + create_function(&ctx); + preload_constants(&ctx); + preload_samplers(&ctx); + preload_streamout_buffers(&ctx); + preload_ring_buffers(&ctx); - if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { int i; for (i = 0; i < 4; i++) { - si_shader_ctx.gs_next_vertex[i] = + ctx.gs_next_vertex[i] = lp_build_alloca(bld_base->base.gallivm, - bld_base->uint_bld.elem_type, ""); + ctx.i32, ""); } } @@ -4503,19 +4480,19 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, /* Dump LLVM IR before any optimization passes */ if (sscreen->b.debug_flags & DBG_PREOPT_IR && - r600_can_dump_shader(&sscreen->b, si_shader_ctx.type)) + r600_can_dump_shader(&sscreen->b, ctx.type)) LLVMDumpModule(mod); - radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld); + radeon_llvm_finalize_module(&ctx.radeon_bld); r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm, - mod, debug, si_shader_ctx.type, "TGSI shader"); + mod, debug, ctx.type, "TGSI shader"); if (r) { fprintf(stderr, "LLVM failed to compile shader\n"); goto out; } - si_shader_dump(sscreen, shader, debug, si_shader_ctx.type); + si_shader_dump(sscreen, shader, debug, ctx.type); r = si_shader_binary_upload(sscreen, shader); if (r) { @@ -4523,13 +4500,13 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, goto out; } - radeon_llvm_dispose(&si_shader_ctx.radeon_bld); + radeon_llvm_dispose(&ctx.radeon_bld); - if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) { + if (ctx.type == TGSI_PROCESSOR_GEOMETRY) { shader->gs_copy_shader = CALLOC_STRUCT(si_shader); shader->gs_copy_shader->selector = shader->selector; - si_shader_ctx.shader = shader->gs_copy_shader; - if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx, + ctx.shader = shader->gs_copy_shader; + if ((r = si_generate_gs_copy_shader(sscreen, &ctx, shader, debug))) { free(shader->gs_copy_shader); shader->gs_copy_shader = NULL; @@ -4539,7 +4516,7 @@ int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm, out: for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++) - FREE(si_shader_ctx.constants[i]); + FREE(ctx.constants[i]); if (poly_stipple) tgsi_free_tokens(tokens); return r; diff --git a/src/gallium/drivers/softpipe/Makefile.am b/src/gallium/drivers/softpipe/Makefile.am index 05126a5dbaf..fd77edc51a1 100644 --- a/src/gallium/drivers/softpipe/Makefile.am +++ b/src/gallium/drivers/softpipe/Makefile.am @@ -25,7 +25,7 @@ include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ $(GALLIUM_DRIVER_CFLAGS) \ - $(MSVC2008_COMPAT_CFLAGS) + $(MSVC2013_COMPAT_CFLAGS) noinst_LTLIBRARIES = libsoftpipe.la diff --git a/src/gallium/drivers/softpipe/SConscript b/src/gallium/drivers/softpipe/SConscript index dc3542c5100..8ae53b676ce 100644 --- a/src/gallium/drivers/softpipe/SConscript +++ b/src/gallium/drivers/softpipe/SConscript @@ -2,7 +2,7 @@ Import('*') env = env.Clone() -env.MSVC2008Compat() +env.MSVC2013Compat() softpipe = env.ConvenienceLibrary( target = 'softpipe', diff --git a/src/gallium/drivers/trace/Makefile.am b/src/gallium/drivers/trace/Makefile.am index 6a8a74a9103..5640192337e 100644 --- a/src/gallium/drivers/trace/Makefile.am +++ b/src/gallium/drivers/trace/Makefile.am @@ -3,7 +3,7 @@ include $(top_srcdir)/src/gallium/Automake.inc AM_CFLAGS = \ $(GALLIUM_DRIVER_CFLAGS) \ - $(MSVC2008_COMPAT_CFLAGS) + $(MSVC2013_COMPAT_CFLAGS) noinst_LTLIBRARIES = libtrace.la diff --git a/src/gallium/drivers/trace/SConscript b/src/gallium/drivers/trace/SConscript index 1bbed73903d..7397983647a 100644 --- a/src/gallium/drivers/trace/SConscript +++ b/src/gallium/drivers/trace/SConscript @@ -2,7 +2,7 @@ Import('*') env = env.Clone() -env.MSVC2008Compat() +env.MSVC2013Compat() trace = env.ConvenienceLibrary( target = 'trace', diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c index dab27dfba96..fc7562d8f57 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c @@ -174,10 +174,9 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws) goto fail; } - /* LLVM 3.6 is required for VI. */ + /* LLVM 3.6.1 is required for VI. */ if (ws->info.chip_class >= VI && - (HAVE_LLVM < 0x0306 || - (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1))) { + HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 1) { fprintf(stderr, "amdgpu: LLVM 3.6.1 is required, got LLVM %i.%i.%i\n", HAVE_LLVM >> 8, HAVE_LLVM & 255, MESA_LLVM_VERSION_PATCH); goto fail; diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h b/src/mesa/drivers/dri/i965/brw_compiler.h index cd28bbb6bbf..fb5740114dc 100644 --- a/src/mesa/drivers/dri/i965/brw_compiler.h +++ b/src/mesa/drivers/dri/i965/brw_compiler.h @@ -387,6 +387,9 @@ struct brw_wm_prog_data { bool uses_pos_offset; bool uses_omask; bool uses_kill; + bool uses_src_depth; + bool uses_src_w; + bool uses_sample_mask; bool pulls_bary; uint32_t prog_offset_16; @@ -626,6 +629,8 @@ struct brw_gs_prog_data { struct brw_vue_prog_data base; + unsigned vertices_in; + /** * Size of an output vertex, measured in HWORDS (32 bytes). */ diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 63d6987d240..7e161e8bb48 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -4790,7 +4790,7 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) case IMM: switch (inst->src[i].type) { case BRW_REGISTER_TYPE_F: - fprintf(file, "%ff", inst->src[i].f); + fprintf(file, "%-gf", inst->src[i].f); break; case BRW_REGISTER_TYPE_W: case BRW_REGISTER_TYPE_D: @@ -4898,10 +4898,12 @@ fs_visitor::get_instruction_generating_reg(fs_inst *start, } void -fs_visitor::setup_payload_gen6() +fs_visitor::setup_fs_payload_gen6() { - bool uses_depth = - (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0; + assert(stage == MESA_SHADER_FRAGMENT); + brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; + brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; + unsigned barycentric_interp_modes = (stage == MESA_SHADER_FRAGMENT) ? ((brw_wm_prog_data*) this->prog_data)->barycentric_interp_modes : 0; @@ -4930,7 +4932,9 @@ fs_visitor::setup_payload_gen6() } /* R27: interpolated depth if uses source depth */ - if (uses_depth) { + prog_data->uses_src_depth = + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0; + if (prog_data->uses_src_depth) { payload.source_depth_reg = payload.num_regs; payload.num_regs++; if (dispatch_width == 16) { @@ -4938,8 +4942,11 @@ fs_visitor::setup_payload_gen6() payload.num_regs++; } } + /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */ - if (uses_depth) { + prog_data->uses_src_w = + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0; + if (prog_data->uses_src_w) { payload.source_w_reg = payload.num_regs; payload.num_regs++; if (dispatch_width == 16) { @@ -4948,19 +4955,17 @@ fs_visitor::setup_payload_gen6() } } - if (stage == MESA_SHADER_FRAGMENT) { - brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; - brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; - prog_data->uses_pos_offset = key->compute_pos_offset; - /* R31: MSAA position offsets. */ - if (prog_data->uses_pos_offset) { - payload.sample_pos_reg = payload.num_regs; - payload.num_regs++; - } + prog_data->uses_pos_offset = key->compute_pos_offset; + /* R31: MSAA position offsets. */ + if (prog_data->uses_pos_offset) { + payload.sample_pos_reg = payload.num_regs; + payload.num_regs++; } /* R32: MSAA input coverage mask */ - if (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) { + prog_data->uses_sample_mask = + (nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0; + if (prog_data->uses_sample_mask) { assert(devinfo->gen >= 7); payload.sample_mask_in_reg = payload.num_regs; payload.num_regs++; @@ -5397,9 +5402,9 @@ fs_visitor::run_fs(bool do_rep_send) assert(stage == MESA_SHADER_FRAGMENT); if (devinfo->gen >= 6) - setup_payload_gen6(); + setup_fs_payload_gen6(); else - setup_payload_gen4(); + setup_fs_payload_gen4(); if (0) { emit_dummy_fs(); diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index ccdf9433798..89fbbfc90e4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -115,8 +115,8 @@ public: bool run_cs(); void optimize(); void allocate_registers(); - void setup_payload_gen4(); - void setup_payload_gen6(); + void setup_fs_payload_gen4(); + void setup_fs_payload_gen6(); void setup_vs_payload(); void setup_gs_payload(); void setup_cs_payload(); diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp b/src/mesa/drivers/dri/i965/brw_link.cpp index f48c6fe12a1..b512f8b6ee1 100644 --- a/src/mesa/drivers/dri/i965/brw_link.cpp +++ b/src/mesa/drivers/dri/i965/brw_link.cpp @@ -27,6 +27,7 @@ #include "brw_nir.h" #include "brw_program.h" #include "compiler/glsl/ir_optimization.h" +#include "compiler/glsl/program.h" #include "program/program.h" #include "main/shaderapi.h" #include "main/uniforms.h" @@ -259,5 +260,6 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg) if (brw->precompile && !brw_shader_precompile(ctx, shProg)) return false; + build_program_resource_list(shProg); return true; } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp index 1b63d568d85..3f30f5b92d1 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp @@ -773,6 +773,8 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, prog_data->output_topology = get_hw_prim_for_gl_prim(shader->info.gs.output_primitive); + prog_data->vertices_in = shader->info.gs.vertices_in; + /* The GLSL linker will have already matched up GS inputs and the outputs * of prior stages. The driver does extend VS outputs in some cases, but * only for legacy OpenGL or Gen4-5 hardware, neither of which offer diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp index 83e1855025d..bfd14f2982d 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_iz.cpp +++ b/src/mesa/drivers/dri/i965/brw_wm_iz.cpp @@ -120,15 +120,14 @@ static const struct { * \param line_aa AA_NEVER, AA_ALWAYS or AA_SOMETIMES * \param lookup bitmask of IZ_* flags */ -void fs_visitor::setup_payload_gen4() +void fs_visitor::setup_fs_payload_gen4() { assert(stage == MESA_SHADER_FRAGMENT); + brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data; brw_wm_prog_key *key = (brw_wm_prog_key*) this->key; GLuint reg = 2; bool kill_stats_promoted_workaround = false; int lookup = key->iz_lookup; - bool uses_depth = - (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0; assert(lookup < IZ_BIT_MAX); @@ -143,7 +142,9 @@ void fs_visitor::setup_payload_gen4() kill_stats_promoted_workaround = true; } - if (wm_iz_table[lookup].sd_present || uses_depth || + prog_data->uses_src_depth = + (nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0; + if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth || kill_stats_promoted_workaround) { payload.source_depth_reg = reg; reg += 2; diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index ec54ef2acd9..6bf0a55e418 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -175,8 +175,7 @@ brw_upload_wm_unit(struct brw_context *brw) } /* BRW_NEW_FRAGMENT_PROGRAM */ - wm->wm5.program_uses_depth = (fp->Base.InputsRead & - (1 << VARYING_SLOT_POS)) != 0; + wm->wm5.program_uses_depth = prog_data->uses_src_depth; wm->wm5.program_computes_depth = (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0; /* _NEW_BUFFERS diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 7def5f5ad3c..128c77ecf0c 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -37,9 +37,6 @@ static void upload_wm_state(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; - /* BRW_NEW_FRAGMENT_PROGRAM */ - const struct brw_fragment_program *fp = - brw_fragment_program_const(brw->fragment_program); /* BRW_NEW_FS_PROG_DATA */ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; bool writes_depth = prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF; @@ -61,8 +58,11 @@ upload_wm_state(struct brw_context *brw) if (ctx->Polygon.StippleFlag) dw1 |= GEN7_WM_POLYGON_STIPPLE_ENABLE; - if (fp->program.Base.InputsRead & VARYING_BIT_POS) - dw1 |= GEN7_WM_USES_SOURCE_DEPTH | GEN7_WM_USES_SOURCE_W; + if (prog_data->uses_src_depth) + dw1 |= GEN7_WM_USES_SOURCE_DEPTH; + + if (prog_data->uses_src_w) + dw1 |= GEN7_WM_USES_SOURCE_W; dw1 |= prog_data->computed_depth_mode << GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT; dw1 |= prog_data->barycentric_interp_modes << @@ -100,7 +100,7 @@ upload_wm_state(struct brw_context *brw) dw2 |= GEN7_WM_MSDISPMODE_PERSAMPLE; } - if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) { + if (prog_data->uses_sample_mask) { dw1 |= GEN7_WM_USES_INPUT_COVERAGE_MASK; } @@ -138,7 +138,6 @@ const struct brw_tracked_state gen7_wm_state = { _NEW_MULTISAMPLE | _NEW_POLYGON, .brw = BRW_NEW_BATCH | - BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA, }, .emit = upload_wm_state, diff --git a/src/mesa/drivers/dri/i965/gen8_gs_state.c b/src/mesa/drivers/dri/i965/gen8_gs_state.c index 6738e85eaba..c3cdb2f4350 100644 --- a/src/mesa/drivers/dri/i965/gen8_gs_state.c +++ b/src/mesa/drivers/dri/i965/gen8_gs_state.c @@ -48,7 +48,7 @@ gen8_upload_gs_state(struct brw_context *brw) OUT_BATCH(_3DSTATE_GS << 16 | (10 - 2)); OUT_BATCH(stage_state->prog_offset); OUT_BATCH(0); - OUT_BATCH(brw->geometry_program->VerticesIn | + OUT_BATCH(brw->gs.prog_data->vertices_in | ((ALIGN(stage_state->sampler_count, 4)/4) << GEN6_GS_SAMPLER_COUNT_SHIFT) | ((prog_data->base.binding_table.size_bytes / 4) << diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 74cdcef015d..b9a06e7b2c7 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -46,14 +46,17 @@ gen8_upload_ps_extra(struct brw_context *brw, if (prog_data->num_varying_inputs != 0) dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE; - if (fp->Base.InputsRead & VARYING_BIT_POS) - dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W; + if (prog_data->uses_src_depth) + dw1 |= GEN8_PSX_USES_SOURCE_DEPTH; + + if (prog_data->uses_src_w) + dw1 |= GEN8_PSX_USES_SOURCE_W; if (multisampled_fbo && _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1) dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE; - if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN) { + if (prog_data->uses_sample_mask) { if (brw->gen >= 9) dw1 |= BRW_PSICMS_INNER << GEN9_PSX_SHADER_NORMAL_COVERAGE_MASK_SHIFT; else diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 889f7cbb5c1..a39693b68f7 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -346,7 +346,8 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_transform_feedback3 = true; ctx->Extensions.ARB_transform_feedback_instanced = true; - if (ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) + if ((brw->gen >= 8 || brw->intelScreen->cmd_parser_version >= 5) && + ctx->Const.MaxComputeWorkGroupSize[0] >= 1024) ctx->Extensions.ARB_compute_shader = true; if (brw->intelScreen->cmd_parser_version >= 2) diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp index 71c5fc4a485..495048d4bfc 100644 --- a/src/mesa/program/ir_to_mesa.cpp +++ b/src/mesa/program/ir_to_mesa.cpp @@ -31,6 +31,7 @@ #include <stdio.h> #include "main/compiler.h" +#include "main/macros.h" #include "main/mtypes.h" #include "main/shaderapi.h" #include "main/shaderobj.h" @@ -3009,6 +3010,7 @@ _mesa_ir_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) _mesa_reference_program(ctx, &linked_prog, NULL); } + build_program_resource_list(prog); return prog->LinkStatus; } @@ -3037,8 +3039,6 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) if (prog->LinkStatus) { if (!ctx->Driver.LinkShader(ctx, prog)) { prog->LinkStatus = GL_FALSE; - } else { - build_program_resource_list(prog); } } diff --git a/src/mesa/state_tracker/st_atom_shader.c b/src/mesa/state_tracker/st_atom_shader.c index 23b7abfc1c5..c8650a5899a 100644 --- a/src/mesa/state_tracker/st_atom_shader.c +++ b/src/mesa/state_tracker/st_atom_shader.c @@ -172,7 +172,8 @@ update_gp( struct st_context *st ) stgp = st_geometry_program(st->ctx->GeometryProgram._Current); assert(stgp->Base.Base.Target == GL_GEOMETRY_PROGRAM_NV); - st->gp_variant = st_get_basic_variant(st, &stgp->tgsi, &stgp->variants); + st->gp_variant = st_get_basic_variant(st, PIPE_SHADER_GEOMETRY, + &stgp->tgsi, &stgp->variants); st_reference_geomprog(st, &st->gp, stgp); @@ -204,7 +205,8 @@ update_tcp( struct st_context *st ) sttcp = st_tessctrl_program(st->ctx->TessCtrlProgram._Current); assert(sttcp->Base.Base.Target == GL_TESS_CONTROL_PROGRAM_NV); - st->tcp_variant = st_get_basic_variant(st, &sttcp->tgsi, &sttcp->variants); + st->tcp_variant = st_get_basic_variant(st, PIPE_SHADER_TESS_CTRL, + &sttcp->tgsi, &sttcp->variants); st_reference_tesscprog(st, &st->tcp, sttcp); @@ -236,7 +238,8 @@ update_tep( struct st_context *st ) sttep = st_tesseval_program(st->ctx->TessEvalProgram._Current); assert(sttep->Base.Base.Target == GL_TESS_EVALUATION_PROGRAM_NV); - st->tep_variant = st_get_basic_variant(st, &sttep->tgsi, &sttep->variants); + st->tep_variant = st_get_basic_variant(st, PIPE_SHADER_TESS_EVAL, + &sttep->tgsi, &sttep->variants); st_reference_tesseprog(st, &st->tep, sttep); diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index ce93aec4e71..2ad91ecf4df 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -34,6 +34,7 @@ #include "compiler/glsl/glsl_parser_extras.h" #include "compiler/glsl/ir_optimization.h" +#include "compiler/glsl/program.h" #include "main/errors.h" #include "main/shaderobj.h" @@ -6148,6 +6149,10 @@ get_mesa_program(struct gl_context *ctx, prog->OutputsWritten, 0ULL, prog->PatchOutputsWritten); count_resources(v, prog); + /* The GLSL IR won't be needed anymore. */ + ralloc_free(shader->ir); + shader->ir = NULL; + /* This must be done before the uniform storage is associated. */ if (shader->Type == GL_FRAGMENT_SHADER && (prog->InputsRead & VARYING_BIT_POS || @@ -6380,6 +6385,8 @@ st_link_shader(struct gl_context *ctx, struct gl_shader_program *prog) validate_ir_tree(ir); } + build_program_resource_list(prog); + for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { struct gl_program *linked_prog; diff --git a/src/mesa/state_tracker/st_program.c b/src/mesa/state_tracker/st_program.c index 624586e6d67..5bd626f8610 100644 --- a/src/mesa/state_tracker/st_program.c +++ b/src/mesa/state_tracker/st_program.c @@ -1271,6 +1271,7 @@ st_translate_geometry_program(struct st_context *st, */ struct st_basic_variant * st_get_basic_variant(struct st_context *st, + unsigned pipe_shader, struct pipe_shader_state *tgsi, struct st_basic_variant **variants) { @@ -1293,7 +1294,22 @@ st_get_basic_variant(struct st_context *st, v = CALLOC_STRUCT(st_basic_variant); if (v) { /* fill in new variant */ - v->driver_shader = pipe->create_gs_state(pipe, tgsi); + switch (pipe_shader) { + case PIPE_SHADER_TESS_CTRL: + v->driver_shader = pipe->create_tcs_state(pipe, tgsi); + break; + case PIPE_SHADER_TESS_EVAL: + v->driver_shader = pipe->create_tes_state(pipe, tgsi); + break; + case PIPE_SHADER_GEOMETRY: + v->driver_shader = pipe->create_gs_state(pipe, tgsi); + break; + default: + assert(!"unhandled shader type"); + free(v); + return NULL; + } + v->key = key; /* insert into list */ @@ -1587,19 +1603,19 @@ st_precompile_shader_variant(struct st_context *st, case GL_TESS_CONTROL_PROGRAM_NV: { struct st_tessctrl_program *p = (struct st_tessctrl_program *)prog; - st_get_basic_variant(st, &p->tgsi, &p->variants); + st_get_basic_variant(st, PIPE_SHADER_TESS_CTRL, &p->tgsi, &p->variants); break; } case GL_TESS_EVALUATION_PROGRAM_NV: { struct st_tesseval_program *p = (struct st_tesseval_program *)prog; - st_get_basic_variant(st, &p->tgsi, &p->variants); + st_get_basic_variant(st, PIPE_SHADER_TESS_EVAL, &p->tgsi, &p->variants); break; } case GL_GEOMETRY_PROGRAM_NV: { struct st_geometry_program *p = (struct st_geometry_program *)prog; - st_get_basic_variant(st, &p->tgsi, &p->variants); + st_get_basic_variant(st, PIPE_SHADER_GEOMETRY, &p->tgsi, &p->variants); break; } diff --git a/src/mesa/state_tracker/st_program.h b/src/mesa/state_tracker/st_program.h index 7717d02cd3f..74f3def6095 100644 --- a/src/mesa/state_tracker/st_program.h +++ b/src/mesa/state_tracker/st_program.h @@ -352,6 +352,7 @@ st_get_fp_variant(struct st_context *st, extern struct st_basic_variant * st_get_basic_variant(struct st_context *st, + unsigned pipe_shader, struct pipe_shader_state *tgsi, struct st_basic_variant **variants); diff --git a/src/util/Makefile.am b/src/util/Makefile.am index e05a2c5958c..093589163ba 100644 --- a/src/util/Makefile.am +++ b/src/util/Makefile.am @@ -38,7 +38,7 @@ libmesautil_la_CPPFLAGS = \ -I$(top_srcdir)/src/gallium/auxiliary \ $(SHA1_CFLAGS) \ $(VISIBILITY_CFLAGS) \ - $(MSVC2008_COMPAT_CFLAGS) + $(MSVC2013_COMPAT_CFLAGS) libmesautil_la_SOURCES = \ $(MESA_UTIL_FILES) \ diff --git a/src/util/SConscript b/src/util/SConscript index 3dbe70a2e8a..5f3ecc1cdfc 100644 --- a/src/util/SConscript +++ b/src/util/SConscript @@ -6,7 +6,7 @@ from sys import executable as python_cmd env = env.Clone() -env.MSVC2008Compat() +env.MSVC2013Compat() env.Prepend(CPPPATH = [ '#include', |