diff options
| -rw-r--r-- | src/gallium/winsys/drm/radeon/core/radeon_buffer.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/src/gallium/winsys/drm/radeon/core/radeon_buffer.c b/src/gallium/winsys/drm/radeon/core/radeon_buffer.c index 3b1c3860a4c..5cbf0dd2c54 100644 --- a/src/gallium/winsys/drm/radeon/core/radeon_buffer.c +++ b/src/gallium/winsys/drm/radeon/core/radeon_buffer.c @@ -217,9 +217,10 @@ static void radeon_buffer_set_tiling(struct radeon_winsys *ws, boolean microtiled, boolean macrotiled) { + struct radeon_winsys_priv *priv = ((struct radeon_winsys *)ws)->priv; struct radeon_pipe_buffer *radeon_buffer = (struct radeon_pipe_buffer*)buffer; - uint32_t flags = 0; + uint32_t flags = 0, old_flags, old_pitch; if (microtiled) { flags |= RADEON_BO_FLAGS_MICRO_TILE; @@ -228,7 +229,17 @@ static void radeon_buffer_set_tiling(struct radeon_winsys *ws, flags |= RADEON_BO_FLAGS_MACRO_TILE; } - radeon_bo_set_tiling(radeon_buffer->bo, flags, pitch); + radeon_bo_get_tiling(radeon_buffer->bo, &old_flags, &old_pitch); + + if (flags != old_flags || pitch != old_pitch) { + /* Tiling determines how DRM treats the buffer data. + * We must flush CS when changing it if the buffer is referenced. */ + if (radeon_bo_is_referenced_by_cs(radeon_buffer->bo, priv->cs)) { + priv->flush_cb(priv->flush_data); + } + + radeon_bo_set_tiling(radeon_buffer->bo, flags, pitch); + } } static void radeon_fence_reference(struct pipe_winsys *ws, |