diff options
| -rw-r--r-- | src/intel/compiler/brw_compiler.h | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 24 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 1 |
4 files changed, 37 insertions, 0 deletions
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 3f383403883..e4c22e31177 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -100,6 +100,12 @@ struct brw_compiler { * This can negatively impact performance. */ bool precise_trig; + + /** + * Is 3DSTATE_CONSTANT_*'s Constant Buffer 0 relative to Dynamic State + * Base Address? (If not, it's a normal GPU address.) + */ + bool constant_buffer_0_is_relative; }; diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index a4794c6a1d2..2a8dbf8cb9a 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1680,4 +1680,10 @@ enum brw_pixel_shader_coverage_mask_mode { # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25) +#define INSTPM 0x20c0 +# define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6) + +#define CS_DEBUG_MODE2 0x20d8 /* Gen9+ */ +# define CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 4) + #endif diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 5e82c1b4ce8..e14ed02e2e1 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -90,6 +90,30 @@ brw_upload_initial_gpu_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } + + /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so + * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address. + * + * On Gen6-7.5, we use an execbuf parameter to do this for us. + * However, the kernel ignores that when execlists are in use. + * Fortunately, we can just write the registers from userspace + * on Gen8+, and they're context saved/restored. + */ + if (brw->gen >= 9) { + BEGIN_BATCH(3); + OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); + OUT_BATCH(CS_DEBUG_MODE2); + OUT_BATCH(REG_MASK(CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE) | + CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE); + ADVANCE_BATCH(); + } else if (brw->gen == 8) { + BEGIN_BATCH(3); + OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); + OUT_BATCH(INSTPM); + OUT_BATCH(REG_MASK(INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE) | + INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE); + ADVANCE_BATCH(); + } } static inline const struct brw_tracked_state * diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 6d0588e9cfa..641edb7e72b 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -2327,6 +2327,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) screen->compiler = brw_compiler_create(screen, devinfo); screen->compiler->shader_debug_log = shader_debug_log_mesa; screen->compiler->shader_perf_log = shader_perf_log_mesa; + screen->compiler->constant_buffer_0_is_relative = devinfo->gen < 8; screen->program_id = 1; screen->has_exec_fence = |