diff options
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.h | 7 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_query.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 2 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_pipe.h | 32 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 8 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 6 | ||||
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_streamout.c | 1 |
7 files changed, 27 insertions, 31 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 5fcaa10afc0..c052a54eb67 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -52,13 +52,6 @@ struct u_log_context; #define R600_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3) #define R600_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4) -#define R600_CONTEXT_STREAMOUT_FLUSH (1u << 0) -/* Pipeline & streamout query controls. */ -#define R600_CONTEXT_START_PIPELINE_STATS (1u << 1) -#define R600_CONTEXT_STOP_PIPELINE_STATS (1u << 2) -#define R600_CONTEXT_FLUSH_FOR_RENDER_COND (1u << 3) -#define R600_CONTEXT_PRIVATE_FLAG (1u << 4) - /* Debug flags. */ enum { /* Shader logging options: */ diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c index 324bc91592e..ded5211ca14 100644 --- a/src/gallium/drivers/radeon/r600_query.c +++ b/src/gallium/drivers/radeon/r600_query.c @@ -1822,7 +1822,7 @@ static void r600_render_condition(struct pipe_context *ctx, /* Settings this in the render cond atom is too late, * so set it here. */ rctx->flags |= rctx->screen->barrier_flags.L2_to_cp | - R600_CONTEXT_FLUSH_FOR_RENDER_COND; + SI_CONTEXT_FLUSH_FOR_RENDER_COND; rctx->render_cond_force_off = old_force_off; } diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index 2d7f6a78c6d..f163e503175 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -191,7 +191,7 @@ void si_begin_new_cs(struct si_context *ctx) ctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 | SI_CONTEXT_INV_ICACHE; - ctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS; + ctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS; /* set all valid group as dirty so they get reemited on * next draw command diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index fd9ba3ae44c..bdf146ff830 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -48,30 +48,34 @@ /* Alignment for optimal CP DMA performance. */ #define SI_CPDMA_ALIGNMENT 32 +/* Pipeline & streamout query controls. */ +#define SI_CONTEXT_START_PIPELINE_STATS (1 << 0) +#define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1) +#define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2) /* Instruction cache. */ -#define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0) +#define SI_CONTEXT_INV_ICACHE (1 << 3) /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */ -#define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1) +#define SI_CONTEXT_INV_SMEM_L1 (1 << 4) /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */ -#define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2) +#define SI_CONTEXT_INV_VMEM_L1 (1 << 5) /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */ -#define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3) +#define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6) /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */ -#define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4) +#define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7) /* Writeback & invalidate the L2 metadata cache. It can only be coupled with * a CB or DB flush. */ -#define SI_CONTEXT_INV_L2_METADATA (R600_CONTEXT_PRIVATE_FLAG << 5) +#define SI_CONTEXT_INV_L2_METADATA (1 << 8) /* Framebuffer caches. */ -#define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6) -#define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7) -#define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8) +#define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9) +#define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10) +#define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11) /* Engine synchronization. */ -#define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9) -#define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10) -#define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11) -#define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12) -#define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13) +#define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12) +#define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13) +#define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14) +#define SI_CONTEXT_VGT_FLUSH (1 << 15) +#define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16) #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0) #define SI_PREFETCH_LS (1 << 1) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index ca32afd25b3..cdab8ea321d 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -1333,11 +1333,11 @@ static void si_set_active_query_state(struct pipe_context *ctx, boolean enable) /* Pipeline stat & streamout queries. */ if (enable) { - sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS; - sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS; + sctx->b.flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS; + sctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS; } else { - sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS; - sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS; + sctx->b.flags &= ~SI_CONTEXT_START_PIPELINE_STATS; + sctx->b.flags |= SI_CONTEXT_STOP_PIPELINE_STATS; } /* Occlusion queries. */ diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 530137ee932..7330bf49983 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -1092,11 +1092,11 @@ void si_emit_cache_flush(struct si_context *sctx) if (cp_coher_cntl) si_emit_surface_sync(rctx, cp_coher_cntl); - if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) { + if (rctx->flags & SI_CONTEXT_START_PIPELINE_STATS) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); - } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) { + } else if (rctx->flags & SI_CONTEXT_STOP_PIPELINE_STATS) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); @@ -1433,7 +1433,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) struct r600_atom *shader_pointers = &sctx->shader_pointers.atom; unsigned masked_atoms = 1u << shader_pointers->id; - if (unlikely(sctx->b.flags & R600_CONTEXT_FLUSH_FOR_RENDER_COND)) + if (unlikely(sctx->b.flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND)) masked_atoms |= 1u << sctx->b.render_cond_atom.id; /* Emit all states except shader pointers and render condition. */ diff --git a/src/gallium/drivers/radeonsi/si_state_streamout.c b/src/gallium/drivers/radeonsi/si_state_streamout.c index 0c20c58df6d..3e83243e954 100644 --- a/src/gallium/drivers/radeonsi/si_state_streamout.c +++ b/src/gallium/drivers/radeonsi/si_state_streamout.c @@ -349,7 +349,6 @@ void si_emit_streamout_end(struct si_context *sctx) } sctx->streamout.begin_emitted = false; - sctx->b.flags |= R600_CONTEXT_STREAMOUT_FLUSH; } /* STREAMOUT CONFIG DERIVED STATE |