diff options
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 16 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 19 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
3 files changed, 20 insertions, 16 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 195a82fef57..8e35dc5299b 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -674,7 +674,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); struct radv_blend_state *blend = &pipeline->graphics.blend; unsigned ps_offset = 0; - unsigned z_order; struct ac_vs_output_info *outinfo; assert (pipeline->shaders[MESA_SHADER_FRAGMENT]); @@ -692,21 +691,8 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, ps->rsrc1); radeon_emit(cmd_buffer->cs, ps->rsrc2); - if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory) - z_order = V_02880C_EARLY_Z_THEN_LATE_Z; - else - z_order = V_02880C_LATE_Z; - - radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL, - S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) | - S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) | - S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) | - S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) | - S_02880C_Z_ORDER(z_order) | - S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) | - S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) | - S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory)); + pipeline->graphics.db_shader_control); radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA, ps->config.spi_ps_input_ena); diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 752986a9c59..42e8abd84ef 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1641,14 +1641,31 @@ radv_pipeline_init(struct radv_pipeline *pipeline, * * Don't add this to CB_SHADER_MASK. */ + struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; if (!pipeline->graphics.blend.spi_shader_col_format) { - struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT]; if (!ps->info.fs.writes_z && !ps->info.fs.writes_stencil && !ps->info.fs.writes_sample_mask) pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; } + unsigned z_order; + pipeline->graphics.db_shader_control = 0; + if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory) + z_order = V_02880C_EARLY_Z_THEN_LATE_Z; + else + z_order = V_02880C_LATE_Z; + + pipeline->graphics.db_shader_control = + S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) | + S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) | + S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) | + S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) | + S_02880C_Z_ORDER(z_order) | + S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) | + S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) | + S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory); + const VkPipelineVertexInputStateCreateInfo *vi_info = pCreateInfo->pVertexInputState; for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) { diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index dcd738a54f4..8e45e95b770 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -955,6 +955,7 @@ struct radv_pipeline { struct radv_depth_stencil_state ds; struct radv_raster_state raster; struct radv_multisample_state ms; + uint32_t db_shader_control; unsigned prim; unsigned gs_out; uint32_t vgt_gs_mode; |