diff options
| -rw-r--r-- | src/amd/compiler/aco_instruction_selection.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 06b8cab7b72..f256ec6eb3a 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2114,12 +2114,13 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) case nir_op_fcos: { Temp src = as_vgpr(ctx, get_alu_src(ctx, instr->src[0])); aco_ptr<Instruction> norm; - Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u)); if (dst.regClass() == v2b) { + Temp half_pi = bld.copy(bld.def(s1), Operand(0x3118u)); Temp tmp = bld.vop2(aco_opcode::v_mul_f16, bld.def(v1), half_pi, src); aco_opcode opcode = instr->op == nir_op_fsin ? aco_opcode::v_sin_f16 : aco_opcode::v_cos_f16; bld.vop1(opcode, Definition(dst), tmp); } else if (dst.regClass() == v1) { + Temp half_pi = bld.copy(bld.def(s1), Operand(0x3e22f983u)); Temp tmp = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), half_pi, src); /* before GFX9, v_sin_f32 and v_cos_f32 had a valid input domain of [-256, +256] */ |