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-rw-r--r--src/mesa/drivers/dri/i965/brw_fs.h2
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_generator.cpp14
-rw-r--r--src/mesa/drivers/dri/i965/gen8_fs_generator.cpp17
3 files changed, 18 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index ba40aef0778..6611c389615 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -700,6 +700,7 @@ private:
struct brw_compile *p;
struct brw_wm_compile *c;
+ const struct brw_wm_prog_key *const key;
struct brw_wm_prog_data *prog_data;
struct gl_shader_program *prog;
@@ -785,6 +786,7 @@ private:
void patch_discard_jumps_to_fb_writes();
struct brw_wm_compile *c;
+ const struct brw_wm_prog_key *const key;
struct brw_wm_prog_data *prog_data;
const struct gl_fragment_program *fp;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index ded8fbdb9e8..99207b3efe4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -42,7 +42,7 @@ fs_generator::fs_generator(struct brw_context *brw,
struct gl_fragment_program *fp,
bool dual_source_output)
- : brw(brw), c(c), prog(prog), fp(fp), dual_source_output(dual_source_output)
+ : brw(brw), c(c), key(&c->key), prog(prog), fp(fp), dual_source_output(dual_source_output)
{
ctx = &brw->ctx;
prog_data = &c->prog_data;
@@ -111,7 +111,7 @@ fs_generator::generate_fb_write(fs_inst *inst)
/* On HSW, the GPU will use the predicate on SENDC, unless the header is
* present.
*/
- if ((fp && fp->UsesKill) || c->key.alpha_test_func) {
+ if ((fp && fp->UsesKill) || key->alpha_test_func) {
struct brw_reg pixel_mask;
if (brw->gen >= 6)
@@ -129,7 +129,7 @@ fs_generator::generate_fb_write(fs_inst *inst)
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- if (inst->target > 0 && c->key.replicate_alpha) {
+ if (inst->target > 0 && key->replicate_alpha) {
/* Set "Source0 Alpha Present to RenderTarget" bit in message
* header.
*/
@@ -648,7 +648,7 @@ fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src
{
unsigned vstride, width;
- if (c->key.high_quality_derivatives) {
+ if (key->high_quality_derivatives) {
/* produce accurate derivatives */
vstride = BRW_VERTICAL_STRIDE_2;
width = BRW_WIDTH_2;
@@ -682,7 +682,7 @@ void
fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
bool negate_value)
{
- if (c->key.high_quality_derivatives) {
+ if (key->high_quality_derivatives) {
/* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
* Region Restrictions):
*
@@ -1702,10 +1702,10 @@ fs_generator::generate_code(exec_list *instructions, FILE *dump_file)
break;
case FS_OPCODE_DDY:
/* Make sure fp->UsesDFdy flag got set (otherwise there's no
- * guarantee that c->key.render_to_fbo is set).
+ * guarantee that key->render_to_fbo is set).
*/
assert(fp->UsesDFdy);
- generate_ddy(inst, dst, src[0], c->key.render_to_fbo);
+ generate_ddy(inst, dst, src[0], key->render_to_fbo);
break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
index f6e4a4bba15..63481b31502 100644
--- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
@@ -40,8 +40,9 @@ gen8_fs_generator::gen8_fs_generator(struct brw_context *brw,
struct gl_shader_program *shader_prog,
struct gl_fragment_program *fp,
bool dual_source_output)
- : gen8_generator(brw, shader_prog, fp ? &fp->Base : NULL, c), c(c), fp(fp),
- dual_source_output(dual_source_output)
+ : gen8_generator(brw, shader_prog, fp ? &fp->Base : NULL, c),
+ c(c), key(&c->key),
+ fp(fp), dual_source_output(dual_source_output)
{
prog_data = &c->prog_data;
}
@@ -72,7 +73,7 @@ gen8_fs_generator::generate_fb_write(fs_inst *ir)
MOV_RAW(brw_message_reg(ir->base_mrf), brw_vec8_grf(0, 0));
gen8_set_exec_size(mov, BRW_EXECUTE_16);
- if (ir->target > 0 && c->key.replicate_alpha) {
+ if (ir->target > 0 && key->replicate_alpha) {
/* Set "Source0 Alpha Present to RenderTarget" bit in the header. */
OR(vec1(retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD)),
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
@@ -116,7 +117,7 @@ gen8_fs_generator::generate_fb_write(fs_inst *ir)
/* "Last Render Target Select" must be set on all writes to the last of
* the render targets (if using MRT), or always for a single RT scenario.
*/
- if ((ir->target == c->key.nr_color_regions - 1) || !c->key.nr_color_regions)
+ if ((ir->target == key->nr_color_regions - 1) || !key->nr_color_regions)
msg_control |= (1 << 4); /* Last Render Target Select */
uint32_t surf_index =
@@ -330,7 +331,7 @@ gen8_fs_generator::generate_ddx(fs_inst *inst,
{
unsigned vstride, width;
- if (c->key.high_quality_derivatives) {
+ if (key->high_quality_derivatives) {
/* Produce accurate derivatives. */
vstride = BRW_VERTICAL_STRIDE_2;
width = BRW_WIDTH_2;
@@ -370,7 +371,7 @@ gen8_fs_generator::generate_ddy(fs_inst *inst,
unsigned src1_swizzle;
unsigned src1_subnr;
- if (c->key.high_quality_derivatives) {
+ if (key->high_quality_derivatives) {
/* Produce accurate derivatives. */
hstride = BRW_HORIZONTAL_STRIDE_1;
src0_swizzle = BRW_SWIZZLE_XYXY;
@@ -1205,10 +1206,10 @@ gen8_fs_generator::generate_code(exec_list *instructions)
break;
case FS_OPCODE_DDY:
/* Make sure fp->UsesDFdy flag got set (otherwise there's no
- * guarantee that c->key.render_to_fbo is set).
+ * guarantee that key->render_to_fbo is set).
*/
assert(fp->UsesDFdy);
- generate_ddy(ir, dst, src[0], c->key.render_to_fbo);
+ generate_ddy(ir, dst, src[0], key->render_to_fbo);
break;
case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 22:54:36 +0000