diff options
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 9 | ||||
| -rw-r--r-- | src/intel/vulkan/genX_state.c | 11 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 5 |
4 files changed, 29 insertions, 0 deletions
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 1c70b2ccbff..4511a075ffc 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -824,6 +824,15 @@ iris_init_render_context(struct iris_screen *screen, iris_upload_slice_hashing_state(batch); #endif +#if GEN_GEN >= 11 + /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM */ + iris_pack_state(GENX(COMMON_SLICE_CHICKEN4), ®_val, reg) { + reg.EnableHardwareFilteringinWM = true; + reg.EnableHardwareFilteringinWMMask = true; + } + iris_emit_lri(batch, COMMON_SLICE_CHICKEN4, reg_val); +#endif + /* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid * changing it dynamically. We set it to the maximum size here, and * instead include the render target dimensions in the viewport, so diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index df76b33a7c3..06b9d497cb0 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -292,6 +292,17 @@ genX(init_device_state)(struct anv_device *device) lri.DataDWord = cache_mode_0; } } + + /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM. */ + uint32_t common_slice_chicken4; + anv_pack_struct(&common_slice_chicken4, GENX(COMMON_SLICE_CHICKEN4), + .EnableHardwareFilteringinWM = true, + .EnableHardwareFilteringinWMMask = true); + + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(COMMON_SLICE_CHICKEN4_num); + lri.DataDWord = common_slice_chicken4; + } #endif /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 76ec9a26a27..5a9e77576ec 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1660,6 +1660,10 @@ enum brw_pixel_shader_coverage_mask_mode { # define GLK_SCEC_BARRIER_MODE_MASK REG_MASK(1 << 7) # define GEN11_STATE_CACHE_REDIRECT_TO_CS_SECTION_ENABLE (1 << 11) + +#define COMMON_SLICE_CHICKEN4 0x7300 +# define GEN11_ENABLE_HARDWARE_FILTERING_IN_WM (1 << 5) + #define HALF_SLICE_CHICKEN7 0xE194 # define TEXEL_OFFSET_FIX_ENABLE (1 << 1) # define TEXEL_OFFSET_FIX_MASK REG_MASK(1 << 1) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 87e459376a8..dfbcea586cc 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -189,6 +189,11 @@ brw_upload_initial_gpu_state(struct brw_context *brw) */ brw_load_register_imm32(brw, GEN8_L3CNTLREG, GEN8_L3CNTLREG_EDBC_NO_HANG); + + /* WA_220160979: Enable Hardware filtering of Semi-Pipelined State in WM */ + brw_load_register_imm32(brw, COMMON_SLICE_CHICKEN4, + GEN11_ENABLE_HARDWARE_FILTERING_IN_WM | + REG_MASK(GEN11_ENABLE_HARDWARE_FILTERING_IN_WM)); } /* hardware specification recommends disabling repacking for |