diff options
| -rw-r--r-- | src/broadcom/qpu/qpu_instr.c | 80 |
1 files changed, 0 insertions, 80 deletions
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c index d5eb2b95dd5..682fee740a0 100644 --- a/src/broadcom/qpu/qpu_instr.c +++ b/src/broadcom/qpu/qpu_instr.c @@ -26,86 +26,6 @@ #include "broadcom/common/v3d_device_info.h" #include "qpu_instr.h" -#ifndef QPU_MASK -#define QPU_MASK(high, low) ((((uint64_t)1<<((high)-(low)+1))-1)<<(low)) -/* Using the GNU statement expression extension */ -#define QPU_SET_FIELD(value, field) \ - ({ \ - uint64_t fieldval = (uint64_t)(value) << field ## _SHIFT; \ - assert((fieldval & ~ field ## _MASK) == 0); \ - fieldval & field ## _MASK; \ - }) - -#define QPU_GET_FIELD(word, field) ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) - -#define QPU_UPDATE_FIELD(inst, value, field) \ - (((inst) & ~(field ## _MASK)) | QPU_SET_FIELD(value, field)) -#endif /* QPU_MASK */ - -#define VC5_QPU_OP_MUL_SHIFT 58 -#define VC5_QPU_OP_MUL_MASK QPU_MASK(63, 58) - -#define VC5_QPU_SIG_SHIFT 53 -#define VC5_QPU_SIG_MASK QPU_MASK(57, 53) - -#define VC5_QPU_COND_SHIFT 46 -#define VC5_QPU_COND_MASK QPU_MASK(52, 46) - -#define VC5_QPU_COND_IFA 0 -#define VC5_QPU_COND_IFB 1 -#define VC5_QPU_COND_IFNA 2 -#define VC5_QPU_COND_IFNB 3 - -#define VC5_QPU_MM QPU_MASK(45, 45) -#define VC5_QPU_MA QPU_MASK(44, 44) - -#define V3D_QPU_WADDR_M_SHIFT 38 -#define V3D_QPU_WADDR_M_MASK QPU_MASK(43, 38) - -#define VC5_QPU_BRANCH_ADDR_LOW_SHIFT 35 -#define VC5_QPU_BRANCH_ADDR_LOW_MASK QPU_MASK(55, 35) - -#define V3D_QPU_WADDR_A_SHIFT 32 -#define V3D_QPU_WADDR_A_MASK QPU_MASK(37, 32) - -#define VC5_QPU_BRANCH_COND_SHIFT 32 -#define VC5_QPU_BRANCH_COND_MASK QPU_MASK(34, 32) - -#define VC5_QPU_BRANCH_ADDR_HIGH_SHIFT 24 -#define VC5_QPU_BRANCH_ADDR_HIGH_MASK QPU_MASK(31, 24) - -#define VC5_QPU_OP_ADD_SHIFT 24 -#define VC5_QPU_OP_ADD_MASK QPU_MASK(31, 24) - -#define VC5_QPU_MUL_B_SHIFT 21 -#define VC5_QPU_MUL_B_MASK QPU_MASK(23, 21) - -#define VC5_QPU_BRANCH_MSFIGN_SHIFT 21 -#define VC5_QPU_BRANCH_MSFIGN_MASK QPU_MASK(22, 21) - -#define VC5_QPU_MUL_A_SHIFT 18 -#define VC5_QPU_MUL_A_MASK QPU_MASK(20, 18) - -#define VC5_QPU_ADD_B_SHIFT 15 -#define VC5_QPU_ADD_B_MASK QPU_MASK(17, 15) - -#define VC5_QPU_BRANCH_BDU_SHIFT 15 -#define VC5_QPU_BRANCH_BDU_MASK QPU_MASK(17, 15) - -#define VC5_QPU_BRANCH_UB QPU_MASK(14, 14) - -#define VC5_QPU_ADD_A_SHIFT 12 -#define VC5_QPU_ADD_A_MASK QPU_MASK(14, 12) - -#define VC5_QPU_BRANCH_BDI_SHIFT 12 -#define VC5_QPU_BRANCH_BDI_MASK QPU_MASK(13, 12) - -#define VC5_QPU_RADDR_A_SHIFT 6 -#define VC5_QPU_RADDR_A_MASK QPU_MASK(11, 6) - -#define VC5_QPU_RADDR_B_SHIFT 0 -#define VC5_QPU_RADDR_B_MASK QPU_MASK(5, 0) - const char * v3d_qpu_magic_waddr_name(enum v3d_qpu_waddr waddr) { |