diff options
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 47 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw.c | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_misc_state.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs.c | 12 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs_state.c | 25 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vs_surface_state.c | 43 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vtbl.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_sampler_state.c | 8 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen6_sampler_state.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen6_vs_state.c | 23 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/gen7_vs_state.c | 18 |
12 files changed, 108 insertions, 85 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index dcd4c9ac701..bd33fd25606 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -818,6 +818,32 @@ struct brw_query_object { /** + * Data shared between brw_context::vs and brw_context::gs + */ +struct brw_stage_state +{ + drm_intel_bo *scratch_bo; + drm_intel_bo *const_bo; + /** Offset in the program cache to the program */ + uint32_t prog_offset; + uint32_t state_offset; + + uint32_t push_const_offset; /* Offset in the batchbuffer */ + int push_const_size; /* in 256-bit register increments */ + + uint32_t bind_bo_offset; + uint32_t surf_offset[BRW_MAX_VEC4_SURFACES]; + + /** SAMPLER_STATE count and table offset */ + uint32_t sampler_count; + uint32_t sampler_offset; + + /** Offsets in the batch to sampler default colors (texture border color) */ + uint32_t sdc_offset[BRW_MAX_TEX_UNIT]; +}; + + +/** * brw_context is derived from gl_context. */ struct brw_context @@ -1141,27 +1167,8 @@ struct brw_context } vec4; struct { + struct brw_stage_state base; struct brw_vs_prog_data *prog_data; - - drm_intel_bo *scratch_bo; - drm_intel_bo *const_bo; - /** Offset in the program cache to the VS program */ - uint32_t prog_offset; - uint32_t state_offset; - - uint32_t push_const_offset; /* Offset in the batchbuffer */ - int push_const_size; /* in 256-bit register increments */ - - uint32_t bind_bo_offset; - uint32_t surf_offset[BRW_MAX_VEC4_SURFACES]; - - /** SAMPLER_STATE count and table offset */ - uint32_t sampler_count; - uint32_t sampler_offset; - - /** Offsets in the batch to sampler default colors (texture border color) - */ - uint32_t sdc_offset[BRW_MAX_TEX_UNIT]; } vs; struct { diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index c7164acfb02..96ba8175ac2 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -376,7 +376,8 @@ static bool brw_try_draw_prims( struct gl_context *ctx, * index. */ brw->wm.sampler_count = _mesa_fls(ctx->FragmentProgram._Current->Base.SamplersUsed); - brw->vs.sampler_count = _mesa_fls(ctx->VertexProgram._Current->Base.SamplersUsed); + brw->vs.base.sampler_count = + _mesa_fls(ctx->VertexProgram._Current->Base.SamplersUsed); /* We have to validate the textures *before* checking for fallbacks; * otherwise, the software fallback won't be able to rely on the diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 3492ea9eaed..16a41ccce4f 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -77,7 +77,7 @@ static void upload_binding_table_pointers(struct brw_context *brw) { BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2)); - OUT_BATCH(brw->vs.bind_bo_offset); + OUT_BATCH(brw->vs.base.bind_bo_offset); OUT_BATCH(0); /* gs */ OUT_BATCH(0); /* clip */ OUT_BATCH(0); /* sf */ @@ -113,7 +113,7 @@ static void upload_gen6_binding_table_pointers(struct brw_context *brw) GEN6_BINDING_TABLE_MODIFY_GS | GEN6_BINDING_TABLE_MODIFY_PS | (4 - 2)); - OUT_BATCH(brw->vs.bind_bo_offset); /* vs */ + OUT_BATCH(brw->vs.base.bind_bo_offset); /* vs */ OUT_BATCH(brw->ff_gs.bind_bo_offset); /* gs */ OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */ ADVANCE_BATCH(); @@ -150,7 +150,7 @@ static void upload_pipelined_state_pointers(struct brw_context *brw ) BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, - brw->vs.state_offset); + brw->vs.base.state_offset); if (brw->ff_gs.prog_active) OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, brw->ff_gs.state_offset | 1); diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c index 43abd891358..364a77a3953 100644 --- a/src/mesa/drivers/dri/i965/brw_vs.c +++ b/src/mesa/drivers/dri/i965/brw_vs.c @@ -299,7 +299,7 @@ do_vs_prog(struct brw_context *brw, prog_data.base.total_scratch = brw_get_scratch_size(c.base.last_scratch*REG_SIZE); - brw_get_scratch_bo(brw, &brw->vs.scratch_bo, + brw_get_scratch_bo(brw, &brw->vs.base.scratch_bo, prog_data.base.total_scratch * brw->max_vs_threads); } @@ -307,7 +307,7 @@ do_vs_prog(struct brw_context *brw, &c.key, sizeof(c.key), program, program_size, &prog_data, sizeof(prog_data), - &brw->vs.prog_offset, &brw->vs.prog_data); + &brw->vs.base.prog_offset, &brw->vs.prog_data); ralloc_free(mem_ctx); return true; @@ -436,7 +436,7 @@ static void brw_upload_vs_prog(struct brw_context *brw) } /* _NEW_TEXTURE */ - brw_populate_sampler_prog_key_data(ctx, prog, brw->vs.sampler_count, + brw_populate_sampler_prog_key_data(ctx, prog, brw->vs.base.sampler_count, &key.base.tex); /* BRW_NEW_VERTICES */ @@ -478,7 +478,7 @@ static void brw_upload_vs_prog(struct brw_context *brw) if (!brw_search_cache(&brw->cache, BRW_VS_PROG, &key, sizeof(key), - &brw->vs.prog_offset, &brw->vs.prog_data)) { + &brw->vs.base.prog_offset, &brw->vs.prog_data)) { bool success = do_vs_prog(brw, ctx->Shader.CurrentVertexProgram, vp, &key); (void) success; @@ -516,7 +516,7 @@ brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog) { struct brw_context *brw = brw_context(ctx); struct brw_vs_prog_key key; - uint32_t old_prog_offset = brw->vs.prog_offset; + uint32_t old_prog_offset = brw->vs.base.prog_offset; struct brw_vs_prog_data *old_prog_data = brw->vs.prog_data; bool success; @@ -546,7 +546,7 @@ brw_vs_precompile(struct gl_context *ctx, struct gl_shader_program *prog) success = do_vs_prog(brw, prog, bvp, &key); - brw->vs.prog_offset = old_prog_offset; + brw->vs.base.prog_offset = old_prog_offset; brw->vs.prog_data = old_prog_data; return success; diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c b/src/mesa/drivers/dri/i965/brw_vs_state.c index e5421f1c3a9..cdffac3b385 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_state.c @@ -39,10 +39,12 @@ static void brw_upload_vs_unit(struct brw_context *brw) { + struct brw_stage_state *stage_state = &brw->vs.base; + struct brw_vs_unit_state *vs; vs = brw_state_batch(brw, AUB_TRACE_VS_STATE, - sizeof(*vs), 32, &brw->vs.state_offset); + sizeof(*vs), 32, &stage_state->state_offset); memset(vs, 0, sizeof(*vs)); /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_VS_PROG */ @@ -50,9 +52,9 @@ brw_upload_vs_unit(struct brw_context *brw) ALIGN(brw->vs.prog_data->base.total_grf, 16) / 16 - 1; vs->thread0.kernel_start_pointer = brw_program_reloc(brw, - brw->vs.state_offset + + stage_state->state_offset + offsetof(struct brw_vs_unit_state, thread0), - brw->vs.prog_offset + + stage_state->prog_offset + (vs->thread0.grf_reg_count << 1)) >> 6; /* Use ALT floating point mode for ARB vertex programs, because they @@ -81,7 +83,7 @@ brw_upload_vs_unit(struct brw_context *brw) if (brw->vs.prog_data->base.total_scratch != 0) { vs->thread2.scratch_space_base_pointer = - brw->vs.scratch_bo->offset >> 10; /* reloc */ + stage_state->scratch_bo->offset >> 10; /* reloc */ vs->thread2.per_thread_scratch_space = ffs(brw->vs.prog_data->base.total_scratch) - 11; } else { @@ -143,7 +145,7 @@ brw_upload_vs_unit(struct brw_context *brw) vs->vs5.sampler_count = 0; /* hardware requirement */ else { /* CACHE_NEW_SAMPLER */ - vs->vs5.sampler_count = (brw->vs.sampler_count + 3) / 4; + vs->vs5.sampler_count = (stage_state->sampler_count + 3) / 4; } @@ -156,23 +158,24 @@ brw_upload_vs_unit(struct brw_context *brw) /* Set the sampler state pointer, and its reloc */ - if (brw->vs.sampler_count) { + if (stage_state->sampler_count) { vs->vs5.sampler_state_pointer = - (brw->batch.bo->offset + brw->vs.sampler_offset) >> 5; + (brw->batch.bo->offset + stage_state->sampler_offset) >> 5; drm_intel_bo_emit_reloc(brw->batch.bo, - brw->vs.state_offset + + stage_state->state_offset + offsetof(struct brw_vs_unit_state, vs5), brw->batch.bo, - brw->vs.sampler_offset | vs->vs5.sampler_count, + (stage_state->sampler_offset | + vs->vs5.sampler_count), I915_GEM_DOMAIN_INSTRUCTION, 0); } /* Emit scratch space relocation */ if (brw->vs.prog_data->base.total_scratch != 0) { drm_intel_bo_emit_reloc(brw->batch.bo, - brw->vs.state_offset + + stage_state->state_offset + offsetof(struct brw_vs_unit_state, thread2), - brw->vs.scratch_bo, + stage_state->scratch_bo, vs->thread2.per_thread_scratch_space, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); } diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c index fe2459f09e5..f1e1a4e602c 100644 --- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c @@ -44,6 +44,8 @@ static void brw_upload_vs_pull_constants(struct brw_context *brw) { + struct brw_stage_state *stage_state = &brw->vs.base; + /* BRW_NEW_VERTEX_PROGRAM */ struct brw_vertex_program *vp = (struct brw_vertex_program *) brw->vertex_program; @@ -56,24 +58,24 @@ brw_upload_vs_pull_constants(struct brw_context *brw) /* CACHE_NEW_VS_PROG */ if (!brw->vs.prog_data->base.nr_pull_params) { - if (brw->vs.const_bo) { - drm_intel_bo_unreference(brw->vs.const_bo); - brw->vs.const_bo = NULL; - brw->vs.surf_offset[SURF_INDEX_VEC4_CONST_BUFFER] = 0; + if (stage_state->const_bo) { + drm_intel_bo_unreference(stage_state->const_bo); + stage_state->const_bo = NULL; + stage_state->surf_offset[SURF_INDEX_VEC4_CONST_BUFFER] = 0; brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF; } return; } /* _NEW_PROGRAM_CONSTANTS */ - drm_intel_bo_unreference(brw->vs.const_bo); + drm_intel_bo_unreference(stage_state->const_bo); uint32_t size = brw->vs.prog_data->base.nr_pull_params * 4; - brw->vs.const_bo = drm_intel_bo_alloc(brw->bufmgr, "vp_const_buffer", - size, 64); + stage_state->const_bo = drm_intel_bo_alloc(brw->bufmgr, "vp_const_buffer", + size, 64); - drm_intel_gem_bo_map_gtt(brw->vs.const_bo); + drm_intel_gem_bo_map_gtt(stage_state->const_bo); for (i = 0; i < brw->vs.prog_data->base.nr_pull_params; i++) { - memcpy(brw->vs.const_bo->virtual + i * 4, + memcpy(stage_state->const_bo->virtual + i * 4, brw->vs.prog_data->base.pull_param[i], 4); } @@ -81,17 +83,17 @@ brw_upload_vs_pull_constants(struct brw_context *brw) if (0) { for (i = 0; i < ALIGN(brw->vs.prog_data->base.nr_pull_params, 4) / 4; i++) { - float *row = (float *)brw->vs.const_bo->virtual + i * 4; + float *row = (float *)stage_state->const_bo->virtual + i * 4; printf("vs const surface %3d: %4.3f %4.3f %4.3f %4.3f\n", i, row[0], row[1], row[2], row[3]); } } - drm_intel_gem_bo_unmap_gtt(brw->vs.const_bo); + drm_intel_gem_bo_unmap_gtt(stage_state->const_bo); const int surf = SURF_INDEX_VEC4_CONST_BUFFER; - brw->vtbl.create_constant_surface(brw, brw->vs.const_bo, 0, size, - &brw->vs.surf_offset[surf], false); + brw->vtbl.create_constant_surface(brw, stage_state->const_bo, 0, size, + &stage_state->surf_offset[surf], false); brw->state.dirty.brw |= BRW_NEW_VS_CONSTBUF; } @@ -108,6 +110,8 @@ const struct brw_tracked_state brw_vs_pull_constants = { static void brw_upload_vs_ubo_surfaces(struct brw_context *brw) { + struct brw_stage_state *stage_state = &brw->vs.base; + struct gl_context *ctx = &brw->ctx; /* _NEW_PROGRAM */ struct gl_shader_program *prog = ctx->Shader.CurrentVertexProgram; @@ -116,7 +120,7 @@ brw_upload_vs_ubo_surfaces(struct brw_context *brw) return; brw_upload_ubo_surfaces(brw, prog->_LinkedShaders[MESA_SHADER_VERTEX], - &brw->vs.surf_offset[SURF_INDEX_VEC4_UBO(0)]); + &stage_state->surf_offset[SURF_INDEX_VEC4_UBO(0)]); } const struct brw_tracked_state brw_vs_ubo_surfaces = { @@ -135,11 +139,12 @@ const struct brw_tracked_state brw_vs_ubo_surfaces = { static void brw_vs_upload_binding_table(struct brw_context *brw) { + struct brw_stage_state *stage_state = &brw->vs.base; uint32_t *bind; int i; if (INTEL_DEBUG & DEBUG_SHADER_TIME) { - gen7_create_shader_time_surface(brw, &brw->vs.surf_offset[SURF_INDEX_VEC4_SHADER_TIME]); + gen7_create_shader_time_surface(brw, &stage_state->surf_offset[SURF_INDEX_VEC4_SHADER_TIME]); } /* CACHE_NEW_VS_PROG: Skip making a binding table if we don't use textures or @@ -147,9 +152,9 @@ brw_vs_upload_binding_table(struct brw_context *brw) */ const unsigned entries = brw->vs.prog_data->base.binding_table_size; if (entries == 0) { - if (brw->vs.bind_bo_offset != 0) { + if (stage_state->bind_bo_offset != 0) { brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE; - brw->vs.bind_bo_offset = 0; + stage_state->bind_bo_offset = 0; } return; } @@ -159,11 +164,11 @@ brw_vs_upload_binding_table(struct brw_context *brw) */ bind = brw_state_batch(brw, AUB_TRACE_BINDING_TABLE, sizeof(uint32_t) * entries, - 32, &brw->vs.bind_bo_offset); + 32, &stage_state->bind_bo_offset); /* BRW_NEW_SURFACES and BRW_NEW_VS_CONSTBUF */ for (i = 0; i < entries; i++) { - bind[i] = brw->vs.surf_offset[i]; + bind[i] = stage_state->surf_offset[i]; } brw->state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE; diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index aee88e0ea4f..43e8167f856 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -81,7 +81,7 @@ brw_destroy_context(struct brw_context *brw) brw_draw_destroy( brw ); dri_bo_release(&brw->curbe.curbe_bo); - dri_bo_release(&brw->vs.const_bo); + dri_bo_release(&brw->vs.base.const_bo); dri_bo_release(&brw->wm.const_bo); free(brw->curbe.last_buf); diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index 1f46f918575..dd5896e4505 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -421,12 +421,14 @@ const struct brw_tracked_state brw_fs_samplers = { static void brw_upload_vs_samplers(struct brw_context *brw) { + struct brw_stage_state *stage_state = &brw->vs.base; + /* BRW_NEW_VERTEX_PROGRAM */ struct gl_program *vs = (struct gl_program *) brw->vertex_program; brw->vtbl.upload_sampler_state_table(brw, vs, - brw->vs.sampler_count, - &brw->vs.sampler_offset, - brw->vs.sdc_offset); + stage_state->sampler_count, + &stage_state->sampler_offset, + stage_state->sdc_offset); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index ea433caaa2d..9f84c93266e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -754,7 +754,7 @@ brw_update_texture_surfaces(struct brw_context *brw) unsigned num_samplers = _mesa_fls(vs->SamplersUsed | fs->SamplersUsed); for (unsigned s = 0; s < num_samplers; s++) { - brw->vs.surf_offset[SURF_INDEX_VEC4_TEXTURE(s)] = 0; + brw->vs.base.surf_offset[SURF_INDEX_VEC4_TEXTURE(s)] = 0; brw->wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0; if (vs->SamplersUsed & (1 << s)) { @@ -763,7 +763,7 @@ brw_update_texture_surfaces(struct brw_context *brw) /* _NEW_TEXTURE */ if (ctx->Texture.Unit[unit]._ReallyEnabled) { brw->vtbl.update_texture_surface(ctx, unit, - brw->vs.surf_offset, + brw->vs.base.surf_offset, SURF_INDEX_VEC4_TEXTURE(s)); } } diff --git a/src/mesa/drivers/dri/i965/gen6_sampler_state.c b/src/mesa/drivers/dri/i965/gen6_sampler_state.c index 16be8a79bfb..5416a179b55 100644 --- a/src/mesa/drivers/dri/i965/gen6_sampler_state.c +++ b/src/mesa/drivers/dri/i965/gen6_sampler_state.c @@ -39,7 +39,7 @@ upload_sampler_state_pointers(struct brw_context *brw) GS_SAMPLER_STATE_CHANGE | PS_SAMPLER_STATE_CHANGE | (4 - 2)); - OUT_BATCH(brw->vs.sampler_offset); /* VS */ + OUT_BATCH(brw->vs.base.sampler_offset); /* VS */ OUT_BATCH(0); /* GS */ OUT_BATCH(brw->wm.sampler_offset); ADVANCE_BATCH(); diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index c5f2fd03a50..0342a22e379 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -37,6 +37,8 @@ static void gen6_upload_vs_push_constants(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; + struct brw_stage_state *stage_state = &brw->vs.base; + /* _BRW_NEW_VERTEX_PROGRAM */ const struct brw_vertex_program *vp = brw_vertex_program_const(brw->vertex_program); @@ -49,7 +51,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw) /* CACHE_NEW_VS_PROG */ if (brw->vs.prog_data->base.nr_params == 0) { - brw->vs.push_const_size = 0; + stage_state->push_const_size = 0; } else { int params_uploaded; float *param; @@ -57,7 +59,7 @@ gen6_upload_vs_push_constants(struct brw_context *brw) param = brw_state_batch(brw, AUB_TRACE_VS_CONSTANTS, brw->vs.prog_data->base.nr_params * sizeof(float), - 32, &brw->vs.push_const_offset); + 32, &stage_state->push_const_offset); /* _NEW_PROGRAM_CONSTANTS * @@ -79,9 +81,9 @@ gen6_upload_vs_push_constants(struct brw_context *brw) } } - brw->vs.push_const_size = (params_uploaded + 1) / 2; + stage_state->push_const_size = (params_uploaded + 1) / 2; /* We can only push 32 registers of constants at a time. */ - assert(brw->vs.push_const_size <= 32); + assert(stage_state->push_const_size <= 32); } } @@ -99,6 +101,7 @@ static void upload_vs_state(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; + const struct brw_stage_state *stage_state = &brw->vs.base; uint32_t floating_point_mode = 0; /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State, @@ -114,7 +117,7 @@ upload_vs_state(struct brw_context *brw) */ intel_emit_post_sync_nonzero_flush(brw); - if (brw->vs.push_const_size == 0) { + if (stage_state->push_const_size == 0) { /* Disable the push constant buffers. */ BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2)); @@ -131,8 +134,8 @@ upload_vs_state(struct brw_context *brw) /* Pointer to the VS constant buffer. Covered by the set of * state flags from gen6_upload_vs_constants */ - OUT_BATCH(brw->vs.push_const_offset + - brw->vs.push_const_size - 1); + OUT_BATCH(stage_state->push_const_offset + + stage_state->push_const_size - 1); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); @@ -147,12 +150,12 @@ upload_vs_state(struct brw_context *brw) BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); - OUT_BATCH(brw->vs.prog_offset); + OUT_BATCH(stage_state->prog_offset); OUT_BATCH(floating_point_mode | - ((ALIGN(brw->vs.sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT)); + ((ALIGN(stage_state->sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT)); if (brw->vs.prog_data->base.total_scratch) { - OUT_RELOC(brw->vs.scratch_bo, + OUT_RELOC(stage_state->scratch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, ffs(brw->vs.prog_data->base.total_scratch) - 11); } else { diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index ce584f675f6..950e2962d75 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -33,6 +33,7 @@ static void upload_vs_state(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; + const struct brw_stage_state *stage_state = &brw->vs.base; uint32_t floating_point_mode = 0; const int max_threads_shift = brw->is_haswell ? HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT; @@ -42,16 +43,16 @@ upload_vs_state(struct brw_context *brw) /* BRW_NEW_VS_BINDING_TABLE */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2)); - OUT_BATCH(brw->vs.bind_bo_offset); + OUT_BATCH(stage_state->bind_bo_offset); ADVANCE_BATCH(); /* CACHE_NEW_SAMPLER */ BEGIN_BATCH(2); OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS_VS << 16 | (2 - 2)); - OUT_BATCH(brw->vs.sampler_offset); + OUT_BATCH(stage_state->sampler_offset); ADVANCE_BATCH(); - if (brw->vs.push_const_size == 0) { + if (stage_state->push_const_size == 0) { /* Disable the push constant buffers. */ BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); @@ -65,12 +66,12 @@ upload_vs_state(struct brw_context *brw) } else { BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); - OUT_BATCH(brw->vs.push_const_size); + OUT_BATCH(stage_state->push_const_size); OUT_BATCH(0); /* Pointer to the VS constant buffer. Covered by the set of * state flags from gen6_prepare_wm_contants */ - OUT_BATCH(brw->vs.push_const_offset | GEN7_MOCS_L3); + OUT_BATCH(stage_state->push_const_offset | GEN7_MOCS_L3); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); @@ -85,12 +86,13 @@ upload_vs_state(struct brw_context *brw) BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); - OUT_BATCH(brw->vs.prog_offset); + OUT_BATCH(stage_state->prog_offset); OUT_BATCH(floating_point_mode | - ((ALIGN(brw->vs.sampler_count, 4)/4) << GEN6_VS_SAMPLER_COUNT_SHIFT)); + ((ALIGN(stage_state->sampler_count, 4)/4) << + GEN6_VS_SAMPLER_COUNT_SHIFT)); if (brw->vs.prog_data->base.total_scratch) { - OUT_RELOC(brw->vs.scratch_bo, + OUT_RELOC(stage_state->scratch_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, ffs(brw->vs.prog_data->base.total_scratch) - 11); } else { |