diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp | 9 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp | 5 |
3 files changed, 4 insertions, 13 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index cd893b16419..61bc868db9e 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -1355,8 +1355,7 @@ brw_compile_tes(const struct brw_compiler *compiler, nir->info->patch_inputs_read = key->patch_inputs_read; struct brw_vue_map input_vue_map; - brw_compute_tess_vue_map(&input_vue_map, - nir->info->inputs_read & ~VARYING_BIT_PRIMITIVE_ID, + brw_compute_tess_vue_map(&input_vue_map, nir->info->inputs_read, nir->info->patch_inputs_read); nir = brw_nir_apply_sampler_key(nir, devinfo, &key->tex, is_scalar); diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp index 2f4306ab581..b2add0378d1 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp @@ -609,12 +609,8 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, * * For SSO pipelines, we use a fixed VUE map layout based on variable * locations, so we can rely on rendezvous-by-location making this work. - * - * However, we need to ignore VARYING_SLOT_PRIMITIVE_ID, as it's not - * written by previous stages and shows up via payload magic. */ - GLbitfield64 inputs_read = - shader->info->inputs_read & ~VARYING_BIT_PRIMITIVE_ID; + GLbitfield64 inputs_read = shader->info->inputs_read; brw_compute_vue_map(compiler->devinfo, &c.input_vue_map, inputs_read, shader->info->separate_shader); @@ -626,8 +622,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data, shader = brw_postprocess_nir(shader, compiler->devinfo, is_scalar); prog_data->include_primitive_id = - (shader->info->inputs_read & VARYING_BIT_PRIMITIVE_ID) || - (shader->info->system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID)); + (shader->info->system_values_read & (1 << SYSTEM_VALUE_PRIMITIVE_ID)) != 0; prog_data->invocations = shader->info->gs.invocations; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp index c6a6b5e1516..da2559c9330 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_tcs.cpp @@ -461,10 +461,7 @@ brw_compile_tcs(const struct brw_compiler *compiler, nir->info->patch_outputs_written = key->patch_outputs_written; struct brw_vue_map input_vue_map; - brw_compute_vue_map(devinfo, &input_vue_map, - nir->info->inputs_read & ~VARYING_BIT_PRIMITIVE_ID, - true); - + brw_compute_vue_map(devinfo, &input_vue_map, nir->info->inputs_read, true); brw_compute_tess_vue_map(&vue_prog_data->vue_map, nir->info->outputs_written, nir->info->patch_outputs_written); |