diff options
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 17 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 10 |
2 files changed, 26 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 2067685c5ab..9e654a511f3 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -179,6 +179,14 @@ static const VkExtensionProperties common_device_extensions[] = { .specVersion = 1, }, }; + +static const VkExtensionProperties rasterization_order_extension[] ={ + { + .extensionName = VK_AMD_RASTERIZATION_ORDER_EXTENSION_NAME, + .specVersion = 1, + }, +}; + static const VkExtensionProperties ext_sema_device_extensions[] = { { .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME, @@ -343,6 +351,15 @@ radv_physical_device_init(struct radv_physical_device *device, if (result != VK_SUCCESS) goto fail; + if (device->rad_info.chip_class >= VI && device->rad_info.max_se >= 2) { + result = radv_extensions_register(instance, + &device->extensions, + rasterization_order_extension, + ARRAY_SIZE(rasterization_order_extension)); + if (result != VK_SUCCESS) + goto fail; + } + if (device->rad_info.has_syncobj) { result = radv_extensions_register(instance, &device->extensions, diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index ee2a2979aaf..2860a003d68 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -33,6 +33,7 @@ #include "nir/nir.h" #include "nir/nir_builder.h" #include "spirv/nir_spirv.h" +#include "vk_util.h" #include <llvm-c/Core.h> #include <llvm-c/TargetMachine.h> @@ -1086,6 +1087,13 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); } + const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = + vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD); + if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) { + ms->pa_sc_mode_cntl_1 |= S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(1) | + S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7); + } + if (vkms) { if (vkms->alphaToCoverageEnable) blend->db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1); @@ -1876,7 +1884,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, !ps->info.fs.writes_sample_mask) pipeline->graphics.blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R; } - + unsigned z_order; pipeline->graphics.db_shader_control = 0; if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory) |