diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_context.c | 14 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_context.h | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_extensions.c | 5 |
5 files changed, 17 insertions, 17 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index f0ee07587fd..48ae942e4de 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -243,10 +243,10 @@ brw_initialize_context_constants(struct brw_context *brw) ctx->Const.UniformBufferOffsetAlignment = 16; ctx->Const.ForceGLSLExtensionsWarn = - driQueryOptionb(&intel->optionCache, "force_glsl_extensions_warn"); + driQueryOptionb(&brw->optionCache, "force_glsl_extensions_warn"); ctx->Const.DisableGLSLLineContinuations = - driQueryOptionb(&intel->optionCache, "disable_glsl_line_continuations"); + driQueryOptionb(&brw->optionCache, "disable_glsl_line_continuations"); /* We want the GLSL compiler to emit code that uses condition codes */ for (int i = 0; i <= MESA_SHADER_FRAGMENT; i++) { @@ -454,7 +454,7 @@ brwCreateContext(int api, brw_draw_init( brw ); - brw->precompile = driQueryOptionb(&intel->optionCache, "shader_precompile"); + brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile"); ctx->Const.ContextFlags = 0; if ((flags & __DRI_CTX_FLAG_FORWARD_COMPATIBLE) != 0) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index f40dcfe421a..f97e19a805f 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -762,6 +762,10 @@ struct brw_query_object { struct brw_context { struct intel_context intel; /**< base class, must be first field */ + + /** drirc option cache */ + driOptionCache optionCache; + GLuint primitive; /**< Hardware primitive, such as _3DPRIM_TRILIST. */ bool emit_state_always; diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c index 2baca61a95a..04ad48d2480 100644 --- a/src/mesa/drivers/dri/i965/intel_context.c +++ b/src/mesa/drivers/dri/i965/intel_context.c @@ -508,7 +508,7 @@ intelInitContext(struct brw_context *brw, memset(&ctx->TextureFormatSupported, 0, sizeof(ctx->TextureFormatSupported)); - driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache, + driParseConfigFiles(&brw->optionCache, &intelScreen->optionCache, sPriv->myNum, "i965"); /* Estimate the size of the mappable aperture into the GTT. There's an @@ -528,7 +528,7 @@ intelInitContext(struct brw_context *brw, intel->bufmgr = intelScreen->bufmgr; - bo_reuse_mode = driQueryOptioni(&intel->optionCache, "bo_reuse"); + bo_reuse_mode = driQueryOptioni(&brw->optionCache, "bo_reuse"); switch (bo_reuse_mode) { case DRI_CONF_BO_REUSE_DISABLED: break; @@ -579,24 +579,24 @@ intelInitContext(struct brw_context *brw, intel_fbo_init(brw); - if (!driQueryOptionb(&intel->optionCache, "hiz")) { + if (!driQueryOptionb(&brw->optionCache, "hiz")) { intel->has_hiz = false; /* On gen6, you can only do separate stencil with HIZ. */ if (intel->gen == 6) intel->has_separate_stencil = false; } - if (driQueryOptionb(&intel->optionCache, "always_flush_batch")) { + if (driQueryOptionb(&brw->optionCache, "always_flush_batch")) { fprintf(stderr, "flushing batchbuffer before/after each draw call\n"); intel->always_flush_batch = 1; } - if (driQueryOptionb(&intel->optionCache, "always_flush_cache")) { + if (driQueryOptionb(&brw->optionCache, "always_flush_cache")) { fprintf(stderr, "flushing GPU caches before/after each draw call\n"); intel->always_flush_cache = 1; } - if (driQueryOptionb(&intel->optionCache, "disable_throttling")) { + if (driQueryOptionb(&brw->optionCache, "disable_throttling")) { fprintf(stderr, "disabling flush throttling\n"); intel->disable_throttling = 1; } @@ -638,7 +638,7 @@ intelDestroyContext(__DRIcontext * driContextPriv) drm_intel_bo_unreference(intel->first_post_swapbuffers_batch); intel->first_post_swapbuffers_batch = NULL; - driDestroyOptionCache(&intel->optionCache); + driDestroyOptionCache(&brw->optionCache); /* free the Mesa context */ _mesa_free_context_data(&intel->ctx); diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index a67c096bd65..f0ce63d6983 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -232,11 +232,6 @@ struct intel_context __DRIcontext *driContext; struct intel_screen *intelScreen; - - /** - * Configuration cache - */ - driOptionCache optionCache; }; /** diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 7468b40ccfc..fa4288c7988 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -39,6 +39,7 @@ void intelInitExtensions(struct gl_context *ctx) { + struct brw_context *brw = brw_context(ctx); struct intel_context *intel = intel_context(ctx); assert(intel->gen >= 4); @@ -135,7 +136,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.EXT_framebuffer_multisample = true; ctx->Extensions.EXT_transform_feedback = true; ctx->Extensions.EXT_framebuffer_multisample_blit_scaled = true; - ctx->Extensions.ARB_blend_func_extended = !driQueryOptionb(&intel->optionCache, "disable_blend_func_extended"); + ctx->Extensions.ARB_blend_func_extended = !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended"); ctx->Extensions.ARB_draw_buffers_blend = true; ctx->Extensions.ARB_ES3_compatibility = true; ctx->Extensions.ARB_uniform_buffer_object = true; @@ -162,7 +163,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_color_buffer_float = true; if (intel->ctx.Mesa_DXTn - || driQueryOptionb(&intel->optionCache, "force_s3tc_enable")) + || driQueryOptionb(&brw->optionCache, "force_s3tc_enable")) ctx->Extensions.EXT_texture_compression_s3tc = true; ctx->Extensions.ANGLE_texture_compression_dxt = true; |