diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c index 9ac0713a1d3..92e5d0fff66 100644 --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c @@ -152,9 +152,6 @@ GLboolean brw_miptree_layout(struct intel_context *intel, * in the texture surfaces run, so they may be "vertical" through * memory. As a result, the docs say in Surface Padding Requirements: * Sampling Engine Surfaces that two extra rows of padding are required. - * We don't know of similar requirements for pre-965, but given that - * those docs are silent on padding requirements in general, let's play - * it safe. */ if (mt->target == GL_TEXTURE_CUBE_MAP) mt->total_height += 2; |