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-rw-r--r--src/gallium/drivers/ilo/genhw/gen_blitter.xml.h2
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h353
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h1
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_regs.xml.h42
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h24
-rw-r--r--src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h4
-rw-r--r--src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c4
-rw-r--r--src/gallium/drivers/ilo/shader/toy_compiler.c4
-rw-r--r--src/gallium/drivers/ilo/shader/toy_legalize.c8
-rw-r--r--src/gallium/drivers/ilo/shader/toy_optimize.c2
-rw-r--r--src/gallium/drivers/ilo/shader/toy_tgsi.c6
11 files changed, 203 insertions, 247 deletions
diff --git a/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h b/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h
index 07e64758aff..94d3136fdb0 100644
--- a/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_blitter.xml.h
@@ -47,8 +47,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN6_BLITTER_BR00_DST_TILED (0x1 << 11)
#define GEN6_BLITTER_LENGTH__MASK 0x0000003f
#define GEN6_BLITTER_LENGTH__SHIFT 0
-#define GEN6_BLITTER_BR13_CLIP_ENABLE (0x1 << 30)
#define GEN6_BLITTER_BR13_DIR_RTL (0x1 << 30)
+#define GEN6_BLITTER_BR13_CLIP_ENABLE (0x1 << 30)
#define GEN6_BLITTER_BR13_FORMAT__MASK 0x03000000
#define GEN6_BLITTER_BR13_FORMAT__SHIFT 24
#define GEN6_BLITTER_BR13_FORMAT_8 (0x0 << 24)
diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h
index e8b85977898..5dcd917c6eb 100644
--- a/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_eu_isa.xml.h
@@ -139,7 +139,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN6_EXECSIZE_8 0x3
#define GEN6_EXECSIZE_16 0x4
#define GEN6_EXECSIZE_32 0x5
-#define GEN6_COND_NORMAL 0x0
+#define GEN6_COND_NONE 0x0
#define GEN6_COND_Z 0x1
#define GEN6_COND_NZ 0x2
#define GEN6_COND_G 0x3
@@ -224,238 +224,153 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN6_ARF_IP 0xa0
#define GEN6_ARF_TDR 0xb0
#define GEN7_ARF_TM0 0xc0
+#define GEN6_INST_SATURATE (0x1 << 31)
+#define GEN6_INST_DEBUGCTRL (0x1 << 30)
+#define GEN6_INST_CMPTCTRL (0x1 << 29)
+#define GEN6_INST_ACCWRCTRL (0x1 << 28)
+#define GEN6_INST_CONDMODIFIER__MASK 0x0f000000
+#define GEN6_INST_CONDMODIFIER__SHIFT 24
+#define GEN6_INST_SFID__MASK 0x0f000000
+#define GEN6_INST_SFID__SHIFT 24
+#define GEN6_INST_FC__MASK 0x0f000000
+#define GEN6_INST_FC__SHIFT 24
+#define GEN6_INST_EXECSIZE__MASK 0x00e00000
+#define GEN6_INST_EXECSIZE__SHIFT 21
+#define GEN6_INST_PREDINV (0x1 << 20)
+#define GEN6_INST_PREDCTRL__MASK 0x000f0000
+#define GEN6_INST_PREDCTRL__SHIFT 16
+#define GEN6_INST_THREADCTRL__MASK 0x0000c000
+#define GEN6_INST_THREADCTRL__SHIFT 14
+#define GEN6_INST_QTRCTRL__MASK 0x00003000
+#define GEN6_INST_QTRCTRL__SHIFT 12
+#define GEN6_INST_DEPCTRL__MASK 0x00000c00
+#define GEN6_INST_DEPCTRL__SHIFT 10
+#define GEN6_INST_MASKCTRL__MASK 0x00000200
+#define GEN6_INST_MASKCTRL__SHIFT 9
+#define GEN6_INST_ACCESSMODE__MASK 0x00000100
+#define GEN6_INST_ACCESSMODE__SHIFT 8
+#define GEN6_INST_OPCODE__MASK 0x0000007f
+#define GEN6_INST_OPCODE__SHIFT 0
+#define GEN6_INST_DST_ADDRMODE__MASK 0x80000000
+#define GEN6_INST_DST_ADDRMODE__SHIFT 31
+#define GEN6_INST_DST_HORZSTRIDE__MASK 0x60000000
+#define GEN6_INST_DST_HORZSTRIDE__SHIFT 29
+#define GEN6_INST_DST_REG__MASK 0x1fe00000
+#define GEN6_INST_DST_REG__SHIFT 21
+#define GEN6_INST_DST_SUBREG__MASK 0x001f0000
+#define GEN6_INST_DST_SUBREG__SHIFT 16
+#define GEN6_INST_DST_ADDR_SUBREG__MASK 0x1c000000
+#define GEN6_INST_DST_ADDR_SUBREG__SHIFT 26
+#define GEN6_INST_DST_ADDR_IMM__MASK 0x03ff0000
+#define GEN6_INST_DST_ADDR_IMM__SHIFT 16
+#define GEN6_INST_DST_SUBREG_ALIGN16__MASK 0x00100000
+#define GEN6_INST_DST_SUBREG_ALIGN16__SHIFT 20
+#define GEN6_INST_DST_SUBREG_ALIGN16__SHR 4
+#define GEN6_INST_DST_ADDR_IMM_ALIGN16__MASK 0x03f00000
+#define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHIFT 20
+#define GEN6_INST_DST_ADDR_IMM_ALIGN16__SHR 4
+#define GEN6_INST_DST_WRITEMASK__MASK 0x000f0000
+#define GEN6_INST_DST_WRITEMASK__SHIFT 16
+#define GEN7_INST_NIBCTRL (0x1 << 15)
+#define GEN6_INST_SRC1_TYPE__MASK 0x00007000
+#define GEN6_INST_SRC1_TYPE__SHIFT 12
+#define GEN6_INST_SRC1_FILE__MASK 0x00000c00
+#define GEN6_INST_SRC1_FILE__SHIFT 10
+#define GEN6_INST_SRC0_TYPE__MASK 0x00000380
+#define GEN6_INST_SRC0_TYPE__SHIFT 7
+#define GEN6_INST_SRC0_FILE__MASK 0x00000060
+#define GEN6_INST_SRC0_FILE__SHIFT 5
+#define GEN6_INST_DST_TYPE__MASK 0x0000001c
+#define GEN6_INST_DST_TYPE__SHIFT 2
+#define GEN6_INST_DST_FILE__MASK 0x00000003
+#define GEN6_INST_DST_FILE__SHIFT 0
+#define GEN7_INST_FLAG_REG__MASK 0x04000000
+#define GEN7_INST_FLAG_REG__SHIFT 26
+#define GEN6_INST_FLAG_SUBREG__MASK 0x02000000
+#define GEN6_INST_FLAG_SUBREG__SHIFT 25
+#define GEN6_INST_SRC_VERTSTRIDE__MASK 0x01e00000
+#define GEN6_INST_SRC_VERTSTRIDE__SHIFT 21
+#define GEN6_INST_SRC_WIDTH__MASK 0x001c0000
+#define GEN6_INST_SRC_WIDTH__SHIFT 18
+#define GEN6_INST_SRC_HORZSTRIDE__MASK 0x00030000
+#define GEN6_INST_SRC_HORZSTRIDE__SHIFT 16
+#define GEN6_INST_SRC_SWIZZLE_W__MASK 0x000c0000
+#define GEN6_INST_SRC_SWIZZLE_W__SHIFT 18
+#define GEN6_INST_SRC_SWIZZLE_Z__MASK 0x00030000
+#define GEN6_INST_SRC_SWIZZLE_Z__SHIFT 16
+#define GEN6_INST_SRC_ADDRMODE__MASK 0x00008000
+#define GEN6_INST_SRC_ADDRMODE__SHIFT 15
+#define GEN6_INST_SRC_NEGATE (0x1 << 14)
+#define GEN6_INST_SRC_ABSOLUTE (0x1 << 13)
+#define GEN6_INST_SRC_REG__MASK 0x00001fe0
+#define GEN6_INST_SRC_REG__SHIFT 5
+#define GEN6_INST_SRC_SUBREG__MASK 0x0000001f
+#define GEN6_INST_SRC_SUBREG__SHIFT 0
+#define GEN6_INST_SRC_ADDR_SUBREG__MASK 0x00001c00
+#define GEN6_INST_SRC_ADDR_SUBREG__SHIFT 10
+#define GEN6_INST_SRC_ADDR_IMM__MASK 0x000003ff
+#define GEN6_INST_SRC_ADDR_IMM__SHIFT 0
+#define GEN6_INST_SRC_SUBREG_ALIGN16__MASK 0x00000010
+#define GEN6_INST_SRC_SUBREG_ALIGN16__SHIFT 4
+#define GEN6_INST_SRC_SUBREG_ALIGN16__SHR 4
+#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__MASK 0x000003f0
+#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHIFT 4
+#define GEN6_INST_SRC_ADDR_IMM_ALIGN16__SHR 4
+#define GEN6_INST_SRC_SWIZZLE_Y__MASK 0x0000000c
+#define GEN6_INST_SRC_SWIZZLE_Y__SHIFT 2
+#define GEN6_INST_SRC_SWIZZLE_X__MASK 0x00000003
+#define GEN6_INST_SRC_SWIZZLE_X__SHIFT 0
+#define GEN6_3SRC_DST_REG__MASK 0xff000000
+#define GEN6_3SRC_DST_REG__SHIFT 24
+#define GEN6_3SRC_DST_SUBREG__MASK 0x00e00000
+#define GEN6_3SRC_DST_SUBREG__SHIFT 21
+#define GEN6_3SRC_DST_SUBREG__SHR 2
+#define GEN6_3SRC_DST_WRITEMASK__MASK 0x001e0000
+#define GEN6_3SRC_DST_WRITEMASK__SHIFT 17
+#define GEN7_3SRC_NIBCTRL (0x1 << 15)
+#define GEN7_3SRC_DST_TYPE__MASK 0x00003000
+#define GEN7_3SRC_DST_TYPE__SHIFT 12
+#define GEN7_3SRC_SRC_TYPE__MASK 0x00000c00
+#define GEN7_3SRC_SRC_TYPE__SHIFT 10
+#define GEN6_3SRC_SRC2_NEGATE (0x1 << 9)
+#define GEN6_3SRC_SRC2_ABSOLUTE (0x1 << 8)
+#define GEN6_3SRC_SRC1_NEGATE (0x1 << 7)
+#define GEN6_3SRC_SRC1_ABSOLUTE (0x1 << 6)
+#define GEN6_3SRC_SRC0_NEGATE (0x1 << 5)
+#define GEN6_3SRC_SRC0_ABSOLUTE (0x1 << 4)
+#define GEN7_3SRC_FLAG_REG__MASK 0x00000004
+#define GEN7_3SRC_FLAG_REG__SHIFT 2
+#define GEN6_3SRC_FLAG_SUBREG__MASK 0x00000002
+#define GEN6_3SRC_FLAG_SUBREG__SHIFT 1
+#define GEN6_3SRC_DST_FILE_MRF (0x1 << 0)
+#define GEN6_3SRC_SRC_REG__MASK 0x000ff000
+#define GEN6_3SRC_SRC_REG__SHIFT 12
+#define GEN6_3SRC_SRC_SUBREG__MASK 0x00000e00
+#define GEN6_3SRC_SRC_SUBREG__SHIFT 9
+#define GEN6_3SRC_SRC_SUBREG__SHR 2
+#define GEN6_3SRC_SRC_SWIZZLE_W__MASK 0x00000180
+#define GEN6_3SRC_SRC_SWIZZLE_W__SHIFT 7
+#define GEN6_3SRC_SRC_SWIZZLE_Z__MASK 0x00000060
+#define GEN6_3SRC_SRC_SWIZZLE_Z__SHIFT 5
+#define GEN6_3SRC_SRC_SWIZZLE_Y__MASK 0x00000018
+#define GEN6_3SRC_SRC_SWIZZLE_Y__SHIFT 3
+#define GEN6_3SRC_SRC_SWIZZLE_X__MASK 0x00000006
+#define GEN6_3SRC_SRC_SWIZZLE_X__SHIFT 1
+#define GEN6_3SRC_SRC_REPCTRL (0x1 << 0)
-#define GEN6_INST_DW0_SATURATE (0x1 << 31)
-#define GEN6_INST_DW0_ACCWRCTRL (0x1 << 28)
-#define GEN6_INST_DW0_CONDMODIFIER__MASK 0x0f000000
-#define GEN6_INST_DW0_CONDMODIFIER__SHIFT 24
-#define GEN6_INST_DW0_SFID__MASK 0x0f000000
-#define GEN6_INST_DW0_SFID__SHIFT 24
-#define GEN6_INST_DW0_FC__MASK 0x0f000000
-#define GEN6_INST_DW0_FC__SHIFT 24
-#define GEN6_INST_DW0_EXECSIZE__MASK 0x00e00000
-#define GEN6_INST_DW0_EXECSIZE__SHIFT 21
-#define GEN6_INST_DW0_PREDINV (0x1 << 20)
-#define GEN6_INST_DW0_PREDCTRL__MASK 0x000f0000
-#define GEN6_INST_DW0_PREDCTRL__SHIFT 16
-#define GEN6_INST_DW0_THREADCTRL__MASK 0x0000c000
-#define GEN6_INST_DW0_THREADCTRL__SHIFT 14
-#define GEN6_INST_DW0_QTRCTRL__MASK 0x00003000
-#define GEN6_INST_DW0_QTRCTRL__SHIFT 12
-#define GEN6_INST_DW0_DEPCTRL__MASK 0x00000c00
-#define GEN6_INST_DW0_DEPCTRL__SHIFT 10
-#define GEN6_INST_DW0_MASKCTRL__MASK 0x00000200
-#define GEN6_INST_DW0_MASKCTRL__SHIFT 9
-#define GEN6_INST_DW0_ACCESSMODE__MASK 0x00000100
-#define GEN6_INST_DW0_ACCESSMODE__SHIFT 8
-#define GEN6_INST_DW0_OPCODE__MASK 0x0000007f
-#define GEN6_INST_DW0_OPCODE__SHIFT 0
-#define GEN6_INST_DW1_ADDRMODE__MASK 0x80000000
-#define GEN6_INST_DW1_ADDRMODE__SHIFT 31
-#define GEN6_INST_DW1_HORZSTRIDE__MASK 0x60000000
-#define GEN6_INST_DW1_HORZSTRIDE__SHIFT 29
-#define GEN6_INST_DW1_REG__MASK 0x1fe00000
-#define GEN6_INST_DW1_REG__SHIFT 21
-#define GEN6_INST_DW1_SUBREG__MASK 0x001f0000
-#define GEN6_INST_DW1_SUBREG__SHIFT 16
-#define GEN6_INST_DW1_ADDR_SUBREG__MASK 0x1c000000
-#define GEN6_INST_DW1_ADDR_SUBREG__SHIFT 26
-#define GEN6_INST_DW1_ADDR_IMM__MASK 0x03ff0000
-#define GEN6_INST_DW1_ADDR_IMM__SHIFT 16
-#define GEN6_INST_DW1_SUBREG_ALIGN16__MASK 0x00100000
-#define GEN6_INST_DW1_SUBREG_ALIGN16__SHIFT 20
-#define GEN6_INST_DW1_SUBREG_ALIGN16__SHR 4
-#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__MASK 0x03f00000
-#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__SHIFT 20
-#define GEN6_INST_DW1_ADDR_IMM_ALIGN16__SHR 4
-#define GEN6_INST_DW1_WRITEMASK__MASK 0x000f0000
-#define GEN6_INST_DW1_WRITEMASK__SHIFT 16
-#define GEN7_INST_DW1_NIBCTRL (0x1 << 15)
-#define GEN6_INST_DW1_SRC1_TYPE__MASK 0x00007000
-#define GEN6_INST_DW1_SRC1_TYPE__SHIFT 12
-#define GEN6_INST_DW1_SRC1_FILE__MASK 0x00000c00
-#define GEN6_INST_DW1_SRC1_FILE__SHIFT 10
-#define GEN6_INST_DW1_SRC0_TYPE__MASK 0x00000380
-#define GEN6_INST_DW1_SRC0_TYPE__SHIFT 7
-#define GEN6_INST_DW1_SRC0_FILE__MASK 0x00000060
-#define GEN6_INST_DW1_SRC0_FILE__SHIFT 5
-#define GEN6_INST_DW1_TYPE__MASK 0x0000001c
-#define GEN6_INST_DW1_TYPE__SHIFT 2
-#define GEN6_INST_DW1_FILE__MASK 0x00000003
-#define GEN6_INST_DW1_FILE__SHIFT 0
-#define GEN7_INST_DW2_FLAG_REG__MASK 0x04000000
-#define GEN7_INST_DW2_FLAG_REG__SHIFT 26
-#define GEN6_INST_DW2_FLAG_SUBREG__MASK 0x02000000
-#define GEN6_INST_DW2_FLAG_SUBREG__SHIFT 25
-#define GEN6_INST_DW2_VERTSTRIDE__MASK 0x01e00000
-#define GEN6_INST_DW2_VERTSTRIDE__SHIFT 21
-#define GEN6_INST_DW2_WIDTH__MASK 0x001c0000
-#define GEN6_INST_DW2_WIDTH__SHIFT 18
-#define GEN6_INST_DW2_HORZSTRIDE__MASK 0x00030000
-#define GEN6_INST_DW2_HORZSTRIDE__SHIFT 16
-#define GEN6_INST_DW2_SWIZZLE_W__MASK 0x000c0000
-#define GEN6_INST_DW2_SWIZZLE_W__SHIFT 18
-#define GEN6_INST_DW2_SWIZZLE_Z__MASK 0x00030000
-#define GEN6_INST_DW2_SWIZZLE_Z__SHIFT 16
-#define GEN6_INST_DW2_ADDRMODE__MASK 0x00008000
-#define GEN6_INST_DW2_ADDRMODE__SHIFT 15
-#define GEN6_INST_DW2_NEGATE (0x1 << 14)
-#define GEN6_INST_DW2_ABSOLUTE (0x1 << 13)
-#define GEN6_INST_DW2_REG__MASK 0x00001fe0
-#define GEN6_INST_DW2_REG__SHIFT 5
-#define GEN6_INST_DW2_SUBREG__MASK 0x0000001f
-#define GEN6_INST_DW2_SUBREG__SHIFT 0
-#define GEN6_INST_DW2_ADDR_SUBREG__MASK 0x00001c00
-#define GEN6_INST_DW2_ADDR_SUBREG__SHIFT 10
-#define GEN6_INST_DW2_ADDR_IMM__MASK 0x000003ff
-#define GEN6_INST_DW2_ADDR_IMM__SHIFT 0
-#define GEN6_INST_DW2_SUBREG_ALIGN16 (0x1 << 4)
-#define GEN6_INST_DW2_SUBREG_ALIGN16__SHR 4
-#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__MASK 0x000003f0
-#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__SHIFT 4
-#define GEN6_INST_DW2_ADDR_IMM_ALIGN16__SHR 4
-#define GEN6_INST_DW2_SWIZZLE_Y__MASK 0x0000000c
-#define GEN6_INST_DW2_SWIZZLE_Y__SHIFT 2
-#define GEN6_INST_DW2_SWIZZLE_X__MASK 0x00000003
-#define GEN6_INST_DW2_SWIZZLE_X__SHIFT 0
-#define GEN7_INST_DW3_FLAG_REG__MASK 0x04000000
-#define GEN7_INST_DW3_FLAG_REG__SHIFT 26
-#define GEN6_INST_DW3_FLAG_SUBREG__MASK 0x02000000
-#define GEN6_INST_DW3_FLAG_SUBREG__SHIFT 25
-#define GEN6_INST_DW3_VERTSTRIDE__MASK 0x01e00000
-#define GEN6_INST_DW3_VERTSTRIDE__SHIFT 21
-#define GEN6_INST_DW3_WIDTH__MASK 0x001c0000
-#define GEN6_INST_DW3_WIDTH__SHIFT 18
-#define GEN6_INST_DW3_HORZSTRIDE__MASK 0x00030000
-#define GEN6_INST_DW3_HORZSTRIDE__SHIFT 16
-#define GEN6_INST_DW3_SWIZZLE_W__MASK 0x000c0000
-#define GEN6_INST_DW3_SWIZZLE_W__SHIFT 18
-#define GEN6_INST_DW3_SWIZZLE_Z__MASK 0x00030000
-#define GEN6_INST_DW3_SWIZZLE_Z__SHIFT 16
-#define GEN6_INST_DW3_ADDRMODE__MASK 0x00008000
-#define GEN6_INST_DW3_ADDRMODE__SHIFT 15
-#define GEN6_INST_DW3_NEGATE (0x1 << 14)
-#define GEN6_INST_DW3_ABSOLUTE (0x1 << 13)
-#define GEN6_INST_DW3_REG__MASK 0x00001fe0
-#define GEN6_INST_DW3_REG__SHIFT 5
-#define GEN6_INST_DW3_SUBREG__MASK 0x0000001f
-#define GEN6_INST_DW3_SUBREG__SHIFT 0
-#define GEN6_INST_DW3_ADDR_SUBREG__MASK 0x00001c00
-#define GEN6_INST_DW3_ADDR_SUBREG__SHIFT 10
-#define GEN6_INST_DW3_ADDR_IMM__MASK 0x000003ff
-#define GEN6_INST_DW3_ADDR_IMM__SHIFT 0
-#define GEN6_INST_DW3_SUBREG_ALIGN16 (0x1 << 4)
-#define GEN6_INST_DW3_SUBREG_ALIGN16__SHR 4
-#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__MASK 0x000003f0
-#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__SHIFT 4
-#define GEN6_INST_DW3_ADDR_IMM_ALIGN16__SHR 4
-#define GEN6_INST_DW3_SWIZZLE_Y__MASK 0x0000000c
-#define GEN6_INST_DW3_SWIZZLE_Y__SHIFT 2
-#define GEN6_INST_DW3_SWIZZLE_X__MASK 0x00000003
-#define GEN6_INST_DW3_SWIZZLE_X__SHIFT 0
-#define GEN6_3SRC_DW0_SATURATE (0x1 << 31)
-#define GEN6_3SRC_DW0_ACCWRCTRL (0x1 << 28)
-#define GEN6_3SRC_DW0_CONDMODIFIER__MASK 0x0f000000
-#define GEN6_3SRC_DW0_CONDMODIFIER__SHIFT 24
-#define GEN6_3SRC_DW0_SFID__MASK 0x0f000000
-#define GEN6_3SRC_DW0_SFID__SHIFT 24
-#define GEN6_3SRC_DW0_FC__MASK 0x0f000000
-#define GEN6_3SRC_DW0_FC__SHIFT 24
-#define GEN6_3SRC_DW0_EXECSIZE__MASK 0x00e00000
-#define GEN6_3SRC_DW0_EXECSIZE__SHIFT 21
-#define GEN6_3SRC_DW0_PREDINV (0x1 << 20)
-#define GEN6_3SRC_DW0_PREDCTRL__MASK 0x000f0000
-#define GEN6_3SRC_DW0_PREDCTRL__SHIFT 16
-#define GEN6_3SRC_DW0_THREADCTRL__MASK 0x0000c000
-#define GEN6_3SRC_DW0_THREADCTRL__SHIFT 14
-#define GEN6_3SRC_DW0_QTRCTRL__MASK 0x00003000
-#define GEN6_3SRC_DW0_QTRCTRL__SHIFT 12
-#define GEN6_3SRC_DW0_DEPCTRL__MASK 0x00000c00
-#define GEN6_3SRC_DW0_DEPCTRL__SHIFT 10
-#define GEN6_3SRC_DW0_MASKCTRL__MASK 0x00000200
-#define GEN6_3SRC_DW0_MASKCTRL__SHIFT 9
-#define GEN6_3SRC_DW0_ACCESSMODE__MASK 0x00000100
-#define GEN6_3SRC_DW0_ACCESSMODE__SHIFT 8
-#define GEN6_3SRC_DW0_OPCODE__MASK 0x0000007f
-#define GEN6_3SRC_DW0_OPCODE__SHIFT 0
-#define GEN6_3SRC_DW1_REG__MASK 0xff000000
-#define GEN6_3SRC_DW1_REG__SHIFT 24
-#define GEN6_3SRC_DW1_SUBREG__MASK 0x00e00000
-#define GEN6_3SRC_DW1_SUBREG__SHIFT 21
-#define GEN6_3SRC_DW1_SUBREG__SHR 2
-#define GEN6_3SRC_DW1_WRITEMASK__MASK 0x001e0000
-#define GEN6_3SRC_DW1_WRITEMASK__SHIFT 17
-#define GEN7_3SRC_DW1_NIBCTRL (0x1 << 15)
-#define GEN7_3SRC_DW1_TYPE__MASK 0x00003000
-#define GEN7_3SRC_DW1_TYPE__SHIFT 12
-#define GEN7_3SRC_DW1_SRC_TYPE__MASK 0x00000c00
-#define GEN7_3SRC_DW1_SRC_TYPE__SHIFT 10
-#define GEN6_3SRC_DW1_SRC2_NEGATE (0x1 << 9)
-#define GEN6_3SRC_DW1_SRC2_ABSOLUTE (0x1 << 8)
-#define GEN6_3SRC_DW1_SRC1_NEGATE (0x1 << 7)
-#define GEN6_3SRC_DW1_SRC1_ABSOLUTE (0x1 << 6)
-#define GEN6_3SRC_DW1_SRC0_NEGATE (0x1 << 5)
-#define GEN6_3SRC_DW1_SRC0_ABSOLUTE (0x1 << 4)
-#define GEN7_3SRC_DW1_FLAG_REG__MASK 0x00000004
-#define GEN7_3SRC_DW1_FLAG_REG__SHIFT 2
-#define GEN6_3SRC_DW1_FLAG_SUBREG__MASK 0x00000002
-#define GEN6_3SRC_DW1_FLAG_SUBREG__SHIFT 1
-#define GEN6_3SRC_DW1_FILE_MRF (0x1 << 0)
#define GEN6_3SRC_SRC_2__MASK 0x7ffffc0000000000ULL
#define GEN6_3SRC_SRC_2__SHIFT 42
-#define GEN6_3SRC_SRC_2_REG__MASK 0x3fc0000000000000ULL
-#define GEN6_3SRC_SRC_2_REG__SHIFT 54
-#define GEN6_3SRC_SRC_2_SUBREG__MASK 0x0038000000000000ULL
-#define GEN6_3SRC_SRC_2_SUBREG__SHIFT 51
-#define GEN6_3SRC_SRC_2_SUBREG__SHR 2
-#define GEN6_3SRC_SRC_2_SWIZZLE_W__MASK 0x0006000000000000ULL
-#define GEN6_3SRC_SRC_2_SWIZZLE_W__SHIFT 49
-#define GEN6_3SRC_SRC_2_SWIZZLE_Z__MASK 0x0001800000000000ULL
-#define GEN6_3SRC_SRC_2_SWIZZLE_Z__SHIFT 47
-#define GEN6_3SRC_SRC_2_SWIZZLE_Y__MASK 0x0000600000000000ULL
-#define GEN6_3SRC_SRC_2_SWIZZLE_Y__SHIFT 45
-#define GEN6_3SRC_SRC_2_SWIZZLE_X__MASK 0x0000180000000000ULL
-#define GEN6_3SRC_SRC_2_SWIZZLE_X__SHIFT 43
-#define GEN6_3SRC_SRC_2_REPCTRL (0x1 << 42)
#define GEN6_3SRC_SRC_1__MASK 0x000003ffffe00000ULL
#define GEN6_3SRC_SRC_1__SHIFT 21
-#define GEN6_3SRC_SRC_1_REG__MASK 0x000001fe00000000ULL
-#define GEN6_3SRC_SRC_1_REG__SHIFT 33
-#define GEN6_3SRC_SRC_1_SUBREG__MASK 0x00000001c0000000ULL
-#define GEN6_3SRC_SRC_1_SUBREG__SHIFT 30
-#define GEN6_3SRC_SRC_1_SUBREG__SHR 2
-#define GEN6_3SRC_SRC_1_SWIZZLE_W__MASK 0x30000000
-#define GEN6_3SRC_SRC_1_SWIZZLE_W__SHIFT 28
-#define GEN6_3SRC_SRC_1_SWIZZLE_Z__MASK 0x0c000000
-#define GEN6_3SRC_SRC_1_SWIZZLE_Z__SHIFT 26
-#define GEN6_3SRC_SRC_1_SWIZZLE_Y__MASK 0x03000000
-#define GEN6_3SRC_SRC_1_SWIZZLE_Y__SHIFT 24
-#define GEN6_3SRC_SRC_1_SWIZZLE_X__MASK 0x00c00000
-#define GEN6_3SRC_SRC_1_SWIZZLE_X__SHIFT 22
-#define GEN6_3SRC_SRC_1_REPCTRL (0x1 << 21)
#define GEN6_3SRC_SRC_0__MASK 0x001fffff
#define GEN6_3SRC_SRC_0__SHIFT 0
-#define GEN6_3SRC_SRC_0_REG__MASK 0x000ff000
-#define GEN6_3SRC_SRC_0_REG__SHIFT 12
-#define GEN6_3SRC_SRC_0_SUBREG__MASK 0x00000e00
-#define GEN6_3SRC_SRC_0_SUBREG__SHIFT 9
-#define GEN6_3SRC_SRC_0_SUBREG__SHR 2
-#define GEN6_3SRC_SRC_0_SWIZZLE_W__MASK 0x00000180
-#define GEN6_3SRC_SRC_0_SWIZZLE_W__SHIFT 7
-#define GEN6_3SRC_SRC_0_SWIZZLE_Z__MASK 0x00000060
-#define GEN6_3SRC_SRC_0_SWIZZLE_Z__SHIFT 5
-#define GEN6_3SRC_SRC_0_SWIZZLE_Y__MASK 0x00000018
-#define GEN6_3SRC_SRC_0_SWIZZLE_Y__SHIFT 3
-#define GEN6_3SRC_SRC_0_SWIZZLE_X__MASK 0x00000006
-#define GEN6_3SRC_SRC_0_SWIZZLE_X__SHIFT 1
-#define GEN6_3SRC_SRC_0_REPCTRL (0x1 << 0)
#endif /* GEN_EU_ISA_XML */
diff --git a/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h
index 36f2097e12b..dd4dd850762 100644
--- a/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_eu_message.xml.h
@@ -205,6 +205,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_8 (0x2 << 8)
#define GEN6_MSG_DP_DWORD_SCATTERED_SIZE_16 (0x3 << 8)
#define GEN6_MSG_DP_RT_LAST (0x1 << 12)
+#define GEN6_MSG_DP_SLOTGRP_HI (0x1 << 11)
#define GEN6_MSG_DP_RT_MODE__MASK 0x00000700
#define GEN6_MSG_DP_RT_MODE__SHIFT 8
#define GEN6_MSG_DP_RT_MODE_SIMD16 (0x0 << 8)
diff --git a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
index 4c59b219765..30ac04ee7c9 100644
--- a/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_regs.xml.h
@@ -35,9 +35,9 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN6_REG_MASK__MASK 0xffff0000
#define GEN6_REG_MASK__SHIFT 16
#define GEN6_REG__SIZE 0x400000
-#define GEN6_REG_HS_INVOCATION_COUNT 0x2300
+#define GEN7_REG_HS_INVOCATION_COUNT 0x2300
-#define GEN6_REG_DS_INVOCATION_COUNT 0x2308
+#define GEN7_REG_DS_INVOCATION_COUNT 0x2308
#define GEN6_REG_IA_VERTICES_COUNT 0x2310
@@ -55,8 +55,46 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN6_REG_PS_INVOCATION_COUNT 0x2348
+#define GEN6_REG_PS_DEPTH_COUNT 0x2350
+
#define GEN6_REG_TIMESTAMP 0x2358
+
+#define GEN7_REG_3DPRIM_END_OFFSET 0x2420
+
+#define GEN7_REG_3DPRIM_START_VERTEX 0x2430
+
+#define GEN7_REG_3DPRIM_VERTEX_COUNT 0x2434
+
+#define GEN7_REG_3DPRIM_INSTANCE_COUNT 0x2438
+
+#define GEN7_REG_3DPRIM_START_INSTANCE 0x243c
+
+#define GEN7_REG_3DPRIM_BASE_VERTEX 0x2440
+
+#define GEN6_REG_OACONTROL 0x2360
+#define GEN6_REG_OACONTROL_COUNTER_SELECT__MASK 0x0000001c
+#define GEN6_REG_OACONTROL_COUNTER_SELECT__SHIFT 2
+#define GEN6_REG_OACONTROL_PERFORMANCE_COUNTER_ENABLE (0x1 << 0)
+
+
+#define GEN6_REG_SO_PRIM_STORAGE_NEEDED 0x2280
+
+#define GEN6_REG_SO_NUM_PRIMS_WRITTEN 0x2288
+
+
+#define GEN7_REG_SO_NUM_PRIMS_WRITTEN(i0) (0x5200 + 0x8*(i0))
+#define GEN7_REG_SO_NUM_PRIMS_WRITTEN__ESIZE 0x8
+#define GEN7_REG_SO_NUM_PRIMS_WRITTEN__LEN 0x4
+
+#define GEN7_REG_SO_PRIM_STORAGE_NEEDED(i0) (0x5240 + 0x8*(i0))
+#define GEN7_REG_SO_PRIM_STORAGE_NEEDED__ESIZE 0x8
+#define GEN7_REG_SO_PRIM_STORAGE_NEEDED__LEN 0x4
+
+#define GEN7_REG_SO_WRITE_OFFSET(i0) (0x5280 + 0x8*(i0))
+#define GEN7_REG_SO_WRITE_OFFSET__ESIZE 0x8
+#define GEN7_REG_SO_WRITE_OFFSET__LEN 0x4
+
#define GEN6_REG_BCS_SWCTRL 0x22200
#define GEN6_REG_BCS_SWCTRL_DST_TILING_Y (0x1 << 1)
#define GEN6_REG_BCS_SWCTRL_SRC_TILING_Y (0x1 << 0)
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
index efbede7f1fd..ccca0dbfc7a 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_3d.xml.h
@@ -85,18 +85,18 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN7_3DPRIM_PATCHLIST_30 0x3d
#define GEN7_3DPRIM_PATCHLIST_31 0x3e
#define GEN7_3DPRIM_PATCHLIST_32 0x3f
-#define GEN6_ALIGNMENT_COLOR_CALC_STATE 0x10
-#define GEN6_ALIGNMENT_DEPTH_STENCIL_STATE 0x10
-#define GEN6_ALIGNMENT_BLEND_STATE 0x10
-#define GEN6_ALIGNMENT_CLIP_VIEWPORT 0x8
-#define GEN6_ALIGNMENT_SF_VIEWPORT 0x8
-#define GEN7_ALIGNMENT_SF_CLIP_VIEWPORT 0x10
-#define GEN6_ALIGNMENT_CC_VIEWPORT 0x8
-#define GEN6_ALIGNMENT_SCISSOR_RECT 0x8
-#define GEN6_ALIGNMENT_BINDING_TABLE_STATE 0x8
-#define GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR 0x8
-#define GEN6_ALIGNMENT_SAMPLER_STATE 0x8
-#define GEN6_ALIGNMENT_SURFACE_STATE 0x8
+#define GEN6_ALIGNMENT_COLOR_CALC_STATE 0x40
+#define GEN6_ALIGNMENT_DEPTH_STENCIL_STATE 0x40
+#define GEN6_ALIGNMENT_BLEND_STATE 0x40
+#define GEN6_ALIGNMENT_CLIP_VIEWPORT 0x20
+#define GEN6_ALIGNMENT_SF_VIEWPORT 0x20
+#define GEN7_ALIGNMENT_SF_CLIP_VIEWPORT 0x40
+#define GEN6_ALIGNMENT_CC_VIEWPORT 0x20
+#define GEN6_ALIGNMENT_SCISSOR_RECT 0x20
+#define GEN6_ALIGNMENT_BINDING_TABLE_STATE 0x20
+#define GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR 0x20
+#define GEN6_ALIGNMENT_SAMPLER_STATE 0x20
+#define GEN6_ALIGNMENT_SURFACE_STATE 0x20
#define GEN6_VFCOMP_NOSTORE 0x0
#define GEN6_VFCOMP_STORE_SRC 0x1
#define GEN6_VFCOMP_STORE_0 0x2
diff --git a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
index f1ffd4ff42e..2d2c07fc04b 100644
--- a/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
+++ b/src/gallium/drivers/ilo/genhw/gen_render_surface.xml.h
@@ -414,6 +414,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN7_SURFACE_DW4_MULTISAMPLECOUNT_8 (0x3 << 3)
#define GEN7_SURFACE_DW4_MSPOS_INDEX__MASK 0x00000007
#define GEN7_SURFACE_DW4_MSPOS_INDEX__SHIFT 0
+#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__MASK 0x07ffffff
+#define GEN7_SURFACE_DW4_MIN_ARRAY_ELEMENT_STRBUF__SHIFT 0
#define GEN7_SURFACE_DW5_X_OFFSET__MASK 0xfe000000
#define GEN7_SURFACE_DW5_X_OFFSET__SHIFT 25
@@ -435,11 +437,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define GEN7_SURFACE_DW6_MCS_ADDR__SHR 12
#define GEN7_SURFACE_DW6_MCS_PITCH__MASK 0x00000ff8
#define GEN7_SURFACE_DW6_MCS_PITCH__SHIFT 3
-#define GEN7_SURFACE_DW6_MCS_ENABLE (0x1 << 0)
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__MASK 0xffffffc0
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHIFT 6
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ADDR__SHR 6
#define GEN7_SURFACE_DW6_APPEND_COUNTER_ENABLE (0x1 << 1)
+#define GEN7_SURFACE_DW6_MCS_ENABLE (0x1 << 0)
#define GEN7_SURFACE_DW7_CC_R__MASK 0x80000000
#define GEN7_SURFACE_DW7_CC_R__SHIFT 31
diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
index 4ff00a17030..4046e63655b 100644
--- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
+++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
@@ -1505,8 +1505,8 @@ ilo_3d_pipeline_emit_write_statistics_gen6(struct ilo_3d_pipeline *p,
GEN6_REG_CL_INVOCATION_COUNT,
GEN6_REG_CL_PRIMITIVES_COUNT,
GEN6_REG_PS_INVOCATION_COUNT,
- p->dev->gen >= ILO_GEN(7) ? GEN6_REG_HS_INVOCATION_COUNT : 0,
- p->dev->gen >= ILO_GEN(7) ? GEN6_REG_DS_INVOCATION_COUNT : 0,
+ p->dev->gen >= ILO_GEN(7) ? GEN7_REG_HS_INVOCATION_COUNT : 0,
+ p->dev->gen >= ILO_GEN(7) ? GEN7_REG_DS_INVOCATION_COUNT : 0,
0,
};
int i;
diff --git a/src/gallium/drivers/ilo/shader/toy_compiler.c b/src/gallium/drivers/ilo/shader/toy_compiler.c
index 6e9dac1bf50..a3e0897f997 100644
--- a/src/gallium/drivers/ilo/shader/toy_compiler.c
+++ b/src/gallium/drivers/ilo/shader/toy_compiler.c
@@ -407,7 +407,7 @@ get_cond_modifier_name(unsigned opcode, unsigned cond_modifier)
break;
default:
switch (cond_modifier) {
- case GEN6_COND_NORMAL: return NULL;
+ case GEN6_COND_NONE: return NULL;
case GEN6_COND_Z: return "z";
case GEN6_COND_NZ: return "nz";
case GEN6_COND_G: return "g";
@@ -515,7 +515,7 @@ tc_init_inst_templ(struct toy_compiler *tc)
templ->pred_ctrl = GEN6_PREDCTRL_NONE;
templ->pred_inv = false;
templ->exec_size = GEN6_EXECSIZE_1;
- templ->cond_modifier = GEN6_COND_NORMAL;
+ templ->cond_modifier = GEN6_COND_NONE;
templ->acc_wr_ctrl = false;
templ->saturate = false;
diff --git a/src/gallium/drivers/ilo/shader/toy_legalize.c b/src/gallium/drivers/ilo/shader/toy_legalize.c
index d632a57da1c..6530c4b6947 100644
--- a/src/gallium/drivers/ilo/shader/toy_legalize.c
+++ b/src/gallium/drivers/ilo/shader/toy_legalize.c
@@ -45,7 +45,7 @@ toy_compiler_lower_to_send(struct toy_compiler *tc, struct toy_inst *inst,
/* thread control is reserved */
assert(inst->thread_ctrl == 0);
- assert(inst->cond_modifier == GEN6_COND_NORMAL);
+ assert(inst->cond_modifier == GEN6_COND_NONE);
inst->cond_modifier = sfid;
}
@@ -98,7 +98,7 @@ toy_compiler_lower_math(struct toy_compiler *tc, struct toy_inst *inst)
}
/* FC[0:3] */
- assert(inst->cond_modifier == GEN6_COND_NORMAL);
+ assert(inst->cond_modifier == GEN6_COND_NONE);
inst->cond_modifier = math_op_to_func(inst->opcode);
/* FC[4:5] */
assert(inst->thread_ctrl == 0);
@@ -567,7 +567,7 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
break;
case GEN6_OPCODE_IF:
if (tc->dev->gen >= ILO_GEN(7) &&
- inst->cond_modifier != GEN6_COND_NORMAL) {
+ inst->cond_modifier != GEN6_COND_NONE) {
struct toy_inst *inst2;
inst2 = tc_duplicate_inst(tc, inst);
@@ -579,7 +579,7 @@ toy_compiler_legalize_for_asm(struct toy_compiler *tc)
inst2->dst = tdst_null();
inst2->src[0] = tsrc_null();
inst2->src[1] = tsrc_null();
- inst2->cond_modifier = GEN6_COND_NORMAL;
+ inst2->cond_modifier = GEN6_COND_NONE;
inst2->pred_ctrl = GEN6_PREDCTRL_NORMAL;
pc++;
diff --git a/src/gallium/drivers/ilo/shader/toy_optimize.c b/src/gallium/drivers/ilo/shader/toy_optimize.c
index 97a04c88632..86fab967cfc 100644
--- a/src/gallium/drivers/ilo/shader/toy_optimize.c
+++ b/src/gallium/drivers/ilo/shader/toy_optimize.c
@@ -55,7 +55,7 @@ eliminate_dead_code(struct toy_compiler *tc)
if (tdst_is_null(inst->dst) || !inst->dst.writemask) {
/* math is always GEN6_COND_NORMAL */
if ((inst->opcode == GEN6_OPCODE_MATH ||
- inst->cond_modifier == GEN6_COND_NORMAL) &&
+ inst->cond_modifier == GEN6_COND_NONE) &&
!inst->acc_wr_ctrl)
tc_discard_inst(tc, inst);
}
diff --git a/src/gallium/drivers/ilo/shader/toy_tgsi.c b/src/gallium/drivers/ilo/shader/toy_tgsi.c
index 08fb10b9273..7c74bad28fc 100644
--- a/src/gallium/drivers/ilo/shader/toy_tgsi.c
+++ b/src/gallium/drivers/ilo/shader/toy_tgsi.c
@@ -111,7 +111,7 @@ aos_simple(struct toy_compiler *tc,
{
struct toy_inst *inst;
int opcode;
- int cond_modifier = GEN6_COND_NORMAL;
+ int cond_modifier = GEN6_COND_NONE;
int num_dst = tgsi_inst->Instruction.NumDstRegs;
int num_src = tgsi_inst->Instruction.NumSrcRegs;
int i;
@@ -284,7 +284,7 @@ aos_compare(struct toy_compiler *tc,
}
tc_CMP(tc, tdst_null(), src[0], zero, GEN6_COND_L);
- inst = tc_SEL(tc, dst[0], src[1], src[2], GEN6_COND_NORMAL);
+ inst = tc_SEL(tc, dst[0], src[1], src[2], GEN6_COND_NONE);
inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
}
@@ -579,7 +579,7 @@ aos_CND(struct toy_compiler *tc,
assert(!"CND untested");
tc_CMP(tc, tdst_null(), src[2], tsrc_imm_f(0.5f), GEN6_COND_G);
- inst = tc_SEL(tc, dst[0], src[0], src[1], GEN6_COND_NORMAL);
+ inst = tc_SEL(tc, dst[0], src[0], src[1], GEN6_COND_NONE);
inst->pred_ctrl = GEN6_PREDCTRL_NORMAL;
}
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-15 19:54:03 +0000