diff options
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_surface_formats.c | 19 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vtbl.c | 22 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_context.h | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_fbo.c | 5 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 |
6 files changed, 26 insertions, 31 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index f54a937cc1e..a1901149200 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1211,6 +1211,9 @@ void brw_upload_ubo_surfaces(struct brw_context *brw, struct gl_shader *shader, uint32_t *surf_offsets); +/* brw_surface_formats.c */ +bool brw_is_hiz_depth_format(struct intel_context *ctx, gl_format format); + /* gen6_sol.c */ void brw_begin_transform_feedback(struct gl_context *ctx, GLenum mode, diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c index c378f02daf9..28a4b3abc12 100644 --- a/src/mesa/drivers/dri/i965/brw_surface_formats.c +++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c @@ -729,3 +729,22 @@ translate_tex_format(struct intel_context *intel, return brw_format_for_mesa_format(mesa_format); } } + +/** Can HiZ be enabled on a depthbuffer of the given format? */ +bool +brw_is_hiz_depth_format(struct intel_context *intel, gl_format format) +{ + if (!intel->has_hiz) + return false; + + switch (format) { + case MESA_FORMAT_Z32_FLOAT: + case MESA_FORMAT_Z32_FLOAT_X24S8: + case MESA_FORMAT_X8_Z24: + case MESA_FORMAT_S8_Z24: + case MESA_FORMAT_Z16: + return true; + default: + return false; + } +} diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index cd51c91c802..0288322e652 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -154,27 +154,6 @@ static void brw_new_batch( struct intel_context *intel ) brw_collect_and_report_shader_time(brw); } -/** - * \see intel_context.vtbl.is_hiz_depth_format - */ -static bool brw_is_hiz_depth_format(struct intel_context *intel, - gl_format format) -{ - if (!intel->has_hiz) - return false; - - switch (format) { - case MESA_FORMAT_Z32_FLOAT: - case MESA_FORMAT_Z32_FLOAT_X24S8: - case MESA_FORMAT_X8_Z24: - case MESA_FORMAT_S8_Z24: - case MESA_FORMAT_Z16: - return true; - default: - return false; - } -} - void brwInitVtbl( struct brw_context *brw ) { brw->intel.vtbl.new_batch = brw_new_batch; @@ -183,7 +162,6 @@ void brwInitVtbl( struct brw_context *brw ) brw->intel.vtbl.debug_batch = brw_debug_batch; brw->intel.vtbl.annotate_aub = brw_annotate_aub; brw->intel.vtbl.render_target_supported = brw_render_target_supported; - brw->intel.vtbl.is_hiz_depth_format = brw_is_hiz_depth_format; assert(brw->intel.gen >= 4); if (brw->intel.gen >= 7) { diff --git a/src/mesa/drivers/dri/i965/intel_context.h b/src/mesa/drivers/dri/i965/intel_context.h index 90a10fa0bf0..19b2f9f0cb3 100644 --- a/src/mesa/drivers/dri/i965/intel_context.h +++ b/src/mesa/drivers/dri/i965/intel_context.h @@ -124,10 +124,6 @@ struct intel_context bool (*render_target_supported)(struct intel_context *intel, struct gl_renderbuffer *rb); - /** Can HiZ be enabled on a depthbuffer of the given format? */ - bool (*is_hiz_depth_format)(struct intel_context *intel, - gl_format format); - void (*update_texture_surface)(struct gl_context *ctx, unsigned unit, uint32_t *binding_table, diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 9ef9b70fff5..a82fb41f598 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -441,8 +441,7 @@ intel_renderbuffer_update_wrapper(struct intel_context *intel, intel_renderbuffer_set_draw_offset(irb); - if (mt->hiz_mt == NULL && - intel->vtbl.is_hiz_depth_format(intel, rb->Format)) { + if (mt->hiz_mt == NULL && brw_is_hiz_depth_format(intel, rb->Format)) { intel_miptree_alloc_hiz(intel, mt); if (!mt->hiz_mt) return false; @@ -862,7 +861,7 @@ intel_renderbuffer_move_to_temp(struct intel_context *intel, irb->mt->num_samples, INTEL_MIPTREE_TILING_ANY); - if (intel->vtbl.is_hiz_depth_format(intel, new_mt->format)) { + if (brw_is_hiz_depth_format(intel, new_mt->format)) { intel_miptree_alloc_hiz(intel, new_mt); } diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index df097d52be8..e9b2464b665 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -369,7 +369,7 @@ intel_miptree_create_layout(struct intel_context *intel, _mesa_get_format_base_format(format) == GL_DEPTH_STENCIL && (intel->must_use_separate_stencil || (intel->has_separate_stencil && - intel->vtbl.is_hiz_depth_format(intel, format)))) { + brw_is_hiz_depth_format(intel, format)))) { mt->stencil_mt = intel_miptree_create(intel, mt->target, MESA_FORMAT_S8, @@ -741,7 +741,7 @@ intel_miptree_create_for_renderbuffer(struct intel_context *intel, if (!mt) goto fail; - if (intel->vtbl.is_hiz_depth_format(intel, format)) { + if (brw_is_hiz_depth_format(intel, format)) { ok = intel_miptree_alloc_hiz(intel, mt); if (!ok) goto fail; |