diff options
| author | Tom Stellard <[email protected]> | 2012-09-24 16:49:43 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-09-24 17:01:31 -0400 |
| commit | 92b033a89ebd46d640ecb2592159087a87e5516e (patch) | |
| tree | 92f373c1ff508ae11170c769b830d804be7996ad /src | |
| parent | 24a8e0c3da65019073f89cb7248916a692707db6 (diff) | |
radeon/llvm: Fix instruction encoding for r600 family GPUs
Tested-by: Michel Dänzer <[email protected]>
https://bugs.freedesktop.org/show_bug.cgi?id=55217
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp | 4 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600Defines.h | 12 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600InstrInfo.h | 13 |
3 files changed, 14 insertions, 15 deletions
diff --git a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp index 847fcb62d4e..a11f48234cb 100644 --- a/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp +++ b/src/gallium/drivers/radeon/MCTargetDesc/R600MCCodeEmitter.cpp @@ -218,8 +218,8 @@ void R600MCCodeEmitter::EmitALUInstr(const MCInst &MI, //older alu have different encoding for instructions with one or two src //parameters. - if (STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst && - MI.getNumOperands() < 4) { + if ((STI.getFeatureBits() & AMDGPU::FeatureR600ALUInst) && + !(MCDesc.TSFlags & R600_InstFlag::OP3)) { uint64_t ISAOpCode = InstWord01 & (0x3FFULL << 39); InstWord01 &= ~(0x3FFULL << 39); InstWord01 |= ISAOpCode << 1; diff --git a/src/gallium/drivers/radeon/R600Defines.h b/src/gallium/drivers/radeon/R600Defines.h index 655b9844592..20c357cc15f 100644 --- a/src/gallium/drivers/radeon/R600Defines.h +++ b/src/gallium/drivers/radeon/R600Defines.h @@ -21,3 +21,15 @@ // operand. #define GET_FLAG_OPERAND_IDX(Flags) (((Flags) >> 7) & 0x3) +namespace R600_InstFlag { + enum TIF { + TRANS_ONLY = (1 << 0), + TEX = (1 << 1), + REDUCTION = (1 << 2), + FC = (1 << 3), + TRIG = (1 << 4), + OP3 = (1 << 5), + VECTOR = (1 << 6) + //FlagOperand bits 7, 8 + }; +} diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h index bfe8d034e35..de82542fa2c 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.h +++ b/src/gallium/drivers/radeon/R600InstrInfo.h @@ -129,17 +129,4 @@ namespace llvm { } // End llvm namespace -namespace R600_InstFlag { - enum TIF { - TRANS_ONLY = (1 << 0), - TEX = (1 << 1), - REDUCTION = (1 << 2), - FC = (1 << 3), - TRIG = (1 << 4), - OP3 = (1 << 5), - VECTOR = (1 << 6) - //FlagOperand bits 7, 8 - }; -} - #endif // R600INSTRINFO_H_ |