diff options
| author | Jason Ekstrand <[email protected]> | 2015-01-13 09:50:37 -0800 |
|---|---|---|
| committer | Jason Ekstrand <[email protected]> | 2015-01-22 10:21:07 -0800 |
| commit | 117a1d69de84c6cb7d895ce7e157f434facde7c9 (patch) | |
| tree | 25c0f383435cedb7e55356f59d4015119d336856 /src | |
| parent | 404660e3c7bc6d13ae1d40185a02bfff6b956ac9 (diff) | |
i965: Apply the miptree offset to surface state for renderbuffers
Previously, we were completely ignoring the mt->offset field for
renderbuffers. While it does have some alignment constraints, it is valid
to use it. This patch adds the code to each of the 4 surface state setup
functions to handle it.
Reviewed-by: Neil Roberts <[email protected]>
Diffstat (limited to 'src')
4 files changed, 8 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 85a08d55232..bf7936caac3 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -658,8 +658,9 @@ brw_update_renderbuffer_surface(struct brw_context *brw, format << BRW_SURFACE_FORMAT_SHIFT); /* reloc */ + assert(mt->offset % mt->cpp == 0); surf[1] = (intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y) + - mt->bo->offset64); + mt->bo->offset64 + mt->offset); surf[2] = ((rb->Width - 1) << BRW_SURFACE_WIDTH_SHIFT | (rb->Height - 1) << BRW_SURFACE_HEIGHT_SHIFT); diff --git a/src/mesa/drivers/dri/i965/gen6_surface_state.c b/src/mesa/drivers/dri/i965/gen6_surface_state.c index 27b441956df..080e0f348fa 100644 --- a/src/mesa/drivers/dri/i965/gen6_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen6_surface_state.c @@ -97,7 +97,8 @@ gen6_update_renderbuffer_surface(struct brw_context *brw, SET_FIELD(format, BRW_SURFACE_FORMAT); /* reloc */ - surf[1] = mt->bo->offset64; + assert(mt->offset % mt->cpp == 0); + surf[1] = mt->bo->offset64 + mt->offset; /* In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 * (Surface Arrays For all surfaces other than separate stencil buffer): diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index e2c347a51ee..68f81d9a6ca 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -517,7 +517,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, surf[0] |= GEN7_SURFACE_IS_ARRAY; } - surf[1] = mt->bo->offset64; + assert(mt->offset % mt->cpp == 0); + surf[1] = mt->bo->offset64 + mt->offset; assert(brw->has_surface_tile_offset); diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c b/src/mesa/drivers/dri/i965/gen8_surface_state.c index d1b095cf535..45c35db0a4d 100644 --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c @@ -432,7 +432,8 @@ gen8_update_renderbuffer_surface(struct brw_context *brw, SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); - *((uint64_t *) &surf[8]) = mt->bo->offset64; /* reloc */ + assert(mt->offset % mt->cpp == 0); + *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */ if (aux_mt) { *((uint64_t *) &surf[10]) = aux_mt->bo->offset64; |