radeonsi: move draw_info to new state handling

Signed-off-by: Christian König <[email protected]>

6 files changed, 84 insertions, 98 deletions

diff --git a/src/gallium/drivers/radeonsi/evergreen_hw_context.c b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
index 9bd547f5477..157fe01abdf 100644
--- a/src/gallium/drivers/radeonsi/evergreen_hw_context.c
+++ b/src/gallium/drivers/radeonsi/evergreen_hw_context.c
@@ -36,7 +36,6 @@ static const struct r600_reg si_config_reg_list[] = {
 	{R_0088B0_VGT_VTX_VECT_EJECT_REG, REG_FLAG_FLUSH_CHANGE},
 	{R_0088C8_VGT_ESGS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
 	{R_0088CC_VGT_GSVS_RING_SIZE, REG_FLAG_FLUSH_CHANGE},
-	{R_008958_VGT_PRIMITIVE_TYPE, 0},
 	{R_008A14_PA_CL_ENHANCE, REG_FLAG_FLUSH_CHANGE},
 	{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
 	{R_00913C_SPI_CONFIG_CNTL_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE},
@@ -52,12 +51,6 @@ static const struct r600_reg si_context_reg_list[] = {
 	{GROUP_FORCE_NEW_BLOCK, 0},
 	{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0},
 	{GROUP_FORCE_NEW_BLOCK, 0},
-	{R_028400_VGT_MAX_VTX_INDX, 0},
-	{R_028404_VGT_MIN_VTX_INDX, 0},
-	{R_028408_VGT_INDX_OFFSET, 0},
-	{R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0},
-	{R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0},
-	{GROUP_FORCE_NEW_BLOCK, 0},
 	{R_028644_SPI_PS_INPUT_CNTL_0, 0},
 	{R_028648_SPI_PS_INPUT_CNTL_1, 0},
 	{R_02864C_SPI_PS_INPUT_CNTL_2, 0},
@@ -104,13 +97,9 @@ static const struct r600_reg si_context_reg_list[] = {
 	{R_0287E0_PA_CL_POINT_CULL_RAD, 0},
 	{R_028804_DB_EQAA, 0},
 	{R_02880C_DB_SHADER_CONTROL, 0},
-	{R_028810_PA_CL_CLIP_CNTL, 0},
-	{R_028814_PA_SU_SC_MODE_CNTL, 0},
-	{R_02881C_PA_CL_VS_OUT_CNTL, 0},
 	{R_028824_PA_SU_LINE_STIPPLE_CNTL, 0},
 	{R_028828_PA_SU_LINE_STIPPLE_SCALE, 0},
 	{R_02882C_PA_SU_PRIM_FILTER_CNTL, 0},
-	{R_028A0C_PA_SC_LINE_STIPPLE, 0},
 	{R_028A10_VGT_OUTPUT_PATH_CNTL, 0},
 	{R_028A14_VGT_HOS_CNTL, 0},
 	{R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0},
diff --git a/src/gallium/drivers/radeonsi/evergreen_state.c b/src/gallium/drivers/radeonsi/evergreen_state.c
index 80dee78988c..354fa6219df 100644
--- a/src/gallium/drivers/radeonsi/evergreen_state.c
+++ b/src/gallium/drivers/radeonsi/evergreen_state.c
@@ -1111,8 +1111,6 @@ void si_init_config(struct r600_context *rctx)
 	r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, NULL, 0);
 	r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, NULL, 0);
 
-	r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
-
 	r600_pipe_state_add_reg(rstate, R_028B54_VGT_SHADER_STAGES_EN, 0, NULL, 0);
 	r600_pipe_state_add_reg(rstate, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210, NULL, 0);
 	r600_pipe_state_add_reg(rstate, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98, NULL, 0);
diff --git a/src/gallium/drivers/radeonsi/r600_state_common.c b/src/gallium/drivers/radeonsi/r600_state_common.c
index a123f09d081..3ad105bc963 100644
--- a/src/gallium/drivers/radeonsi/r600_state_common.c
+++ b/src/gallium/drivers/radeonsi/r600_state_common.c
@@ -92,33 +92,6 @@ void r600_texture_barrier(struct pipe_context *ctx)
 	r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
 }
 
-static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
-{
-	static const int prim_conv[] = {
-		V_008958_DI_PT_POINTLIST,
-		V_008958_DI_PT_LINELIST,
-		V_008958_DI_PT_LINELOOP,
-		V_008958_DI_PT_LINESTRIP,
-		V_008958_DI_PT_TRILIST,
-		V_008958_DI_PT_TRISTRIP,
-		V_008958_DI_PT_TRIFAN,
-		V_008958_DI_PT_QUADLIST,
-		V_008958_DI_PT_QUADSTRIP,
-		V_008958_DI_PT_POLYGON,
-		-1,
-		-1,
-		-1,
-		-1
-	};
-
-	*prim = prim_conv[pprim];
-	if (*prim == -1) {
-		fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
-		return false;
-	}
-	return true;
-}
-
 /* common state between evergreen and r600 */
 void r600_sampler_view_destroy(struct pipe_context *ctx,
 			       struct pipe_sampler_view *state)
@@ -554,14 +527,12 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 	struct pipe_draw_info info = *dinfo;
 	struct r600_draw rdraw = {};
 	struct pipe_index_buffer ib = {};
-	unsigned prim, ls_mask = 0;
 	struct r600_block *dirty_block = NULL, *next_block = NULL;
 	struct r600_atom *state = NULL, *next_state = NULL;
 	int i;
 
 	if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
-	    (info.indexed && !rctx->index_buffer.buffer) ||
-	    !r600_conv_pipe_prim(info.mode, &prim)) {
+	    (info.indexed && !rctx->index_buffer.buffer)) {
 		return;
 	}
 
@@ -611,59 +582,8 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 
 	rctx->vs_shader_so_strides = rctx->vs_shader->so_strides;
 
-	if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
-		rctx->vgt.id = R600_PIPE_STATE_VGT;
-		rctx->vgt.nregs = 0;
-		r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
-#if 0
-		r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
-#endif
-		r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
-		r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0x0, NULL, 0);
-	}
-
-	rctx->vgt.nregs = 0;
-	r600_pipe_state_mod_reg(&rctx->vgt, prim);
-	r600_pipe_state_mod_reg(&rctx->vgt, ~0);
-	r600_pipe_state_mod_reg(&rctx->vgt, 0);
-	r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
-	r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
-	r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
-#if 0
-	r600_pipe_state_mod_reg(&rctx->vgt, 0);
-	r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
-#endif
-
-	if (prim == V_008958_DI_PT_LINELIST)
-		ls_mask = 1;
-	else if (prim == V_008958_DI_PT_LINESTRIP) 
-		ls_mask = 2;
-	r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
-
-	if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
-		r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
-	} else {
-		r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
-	}
-	r600_pipe_state_mod_reg(&rctx->vgt,
-				prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
-				/*| (rctx->rasterizer->clip_plane_enable &
-				  rctx->vs_shader->shader.clip_dist_write)*/);
-	r600_pipe_state_mod_reg(&rctx->vgt,
-				rctx->pa_cl_clip_cntl /*|
-				(rctx->vs_shader->shader.clip_dist_write ||
-				 rctx->vs_shader->shader.vs_prohibit_ucps ?
-				 0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
-
-	r600_context_pipe_state_set(rctx, &rctx->vgt);
+	if (!si_update_draw_info_state(rctx, &info))
+		return;
 
 	rdraw.db_render_override = dsa->db_render_override;
 	rdraw.db_render_control = dsa->db_render_control;
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index 983d3973eeb..ec2a30744ea 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -77,7 +77,6 @@ struct r600_atom_surface_sync {
 enum r600_pipe_state_id {
 	R600_PIPE_STATE_CONFIG,
 	R600_PIPE_STATE_SEAMLESS_CUBEMAP,
-	R600_PIPE_STATE_VGT,
 	R600_PIPE_STATE_PS_SHADER,
 	R600_PIPE_STATE_VS_SHADER,
 	R600_PIPE_STATE_CONSTANT,
@@ -211,7 +210,6 @@ struct r600_context {
 	struct r600_pipe_state		vs_const_buffer;
 	struct r600_pipe_state		vs_user_data;
 	struct r600_pipe_state		ps_const_buffer;
-	struct r600_pipe_state          vgt;
 	struct r600_pipe_state          spi;
 	struct pipe_query		*current_render_cond;
 	unsigned			current_render_cond_mode;
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 1c0fc8a5cd9..ba8724f3de0 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1313,3 +1313,81 @@ void si_init_state_functions(struct r600_context *rctx)
 
 	rctx->context.set_framebuffer_state = si_set_framebuffer_state;
 }
+
+static unsigned si_conv_pipe_prim(unsigned pprim)
+{
+        static const unsigned prim_conv[] = {
+		[PIPE_PRIM_POINTS]			= V_008958_DI_PT_POINTLIST,
+		[PIPE_PRIM_LINES]			= V_008958_DI_PT_LINELIST,
+		[PIPE_PRIM_LINE_LOOP]			= V_008958_DI_PT_LINELOOP,
+		[PIPE_PRIM_LINE_STRIP]			= V_008958_DI_PT_LINESTRIP,
+		[PIPE_PRIM_TRIANGLES]			= V_008958_DI_PT_TRILIST,
+		[PIPE_PRIM_TRIANGLE_STRIP]		= V_008958_DI_PT_TRISTRIP,
+		[PIPE_PRIM_TRIANGLE_FAN]		= V_008958_DI_PT_TRIFAN,
+		[PIPE_PRIM_QUADS]			= V_008958_DI_PT_QUADLIST,
+		[PIPE_PRIM_QUAD_STRIP]			= V_008958_DI_PT_QUADSTRIP,
+		[PIPE_PRIM_POLYGON]			= V_008958_DI_PT_POLYGON,
+		[PIPE_PRIM_LINES_ADJACENCY]		= ~0,
+		[PIPE_PRIM_LINE_STRIP_ADJACENCY]	= ~0,
+		[PIPE_PRIM_TRIANGLES_ADJACENCY]		= ~0,
+		[PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY]	= ~0
+        };
+	unsigned result = prim_conv[pprim];
+        if (result == ~0) {
+		R600_ERR("unsupported primitive type %d\n", pprim);
+        }
+	return result;
+}
+
+bool si_update_draw_info_state(struct r600_context *rctx,
+			       const struct pipe_draw_info *info)
+{
+	struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+	unsigned prim = si_conv_pipe_prim(info->mode);
+	unsigned ls_mask = 0;
+
+	if (pm4 == NULL)
+		return false;
+
+	if (prim == ~0) {
+		FREE(pm4);
+		return false;
+	}
+
+	si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
+	si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
+	si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
+	si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, info->index_bias);
+	si_pm4_set_reg(pm4, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info->restart_index);
+	si_pm4_set_reg(pm4, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
+#if 0
+	si_pm4_set_reg(pm4, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
+	si_pm4_set_reg(pm4, R_03CFF4_SQ_VTX_START_INST_LOC, info->start_instance);
+#endif
+
+        if (prim == V_008958_DI_PT_LINELIST)
+                ls_mask = 1;
+        else if (prim == V_008958_DI_PT_LINESTRIP)
+                ls_mask = 2;
+	si_pm4_set_reg(pm4, R_028A0C_PA_SC_LINE_STIPPLE,
+		       S_028A0C_AUTO_RESET_CNTL(ls_mask) |
+		       rctx->pa_sc_line_stipple);
+
+        if (info->mode == PIPE_PRIM_QUADS || info->mode == PIPE_PRIM_QUAD_STRIP || info->mode == PIPE_PRIM_POLYGON) {
+		si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
+			       S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
+        } else {
+		si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
+        }
+	si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
+		       prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
+		       /*| (rctx->rasterizer->clip_plane_enable &
+		       rctx->vs_shader->shader.clip_dist_write)*/);
+	si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
+			/*| (rctx->vs_shader->shader.clip_dist_write ||
+			rctx->vs_shader->shader.vs_prohibit_ucps ?
+			0 : rctx->rasterizer->clip_plane_enable & 0x3F)*/);
+
+	si_pm4_set_state(rctx, draw_info, pm4);
+	return true;
+}
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index 4034f5514e2..d6c696afb85 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -74,6 +74,7 @@ union si_state {
 		struct si_pm4_state		*fb_rs;
 		struct si_pm4_state		*fb_blend;
 		struct si_pm4_state		*dsa_stencil_ref;
+		struct si_pm4_state		*draw_info;
 	} named;
 	struct si_pm4_state	*array[0];
 };
@@ -106,5 +107,7 @@ union si_state {
 	} while(0);
 
 void si_init_state_functions(struct r600_context *rctx);
+bool si_update_draw_info_state(struct r600_context *rctx,
+			       const struct pipe_draw_info *info);
 
 #endif