diff options
| author | Kenneth Graunke <[email protected]> | 2013-11-04 14:09:07 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-12-02 13:26:03 -0800 |
| commit | decf070258f396223aac6f57e22540a304986e54 (patch) | |
| tree | 77efbe4ef4126fa47c1eddd57688defeb3c8846e /src | |
| parent | 8ed9f69b361a5d6f013d0d8a7f87dba65bfff24a (diff) | |
i965: Skip the register write check on Broadwell.
MI_STORE_REGISTER_MEM has to take a 48-bit address, so the existing code
doesn't work. But supposedly Broadwell has a register whitelist and
just works out of the box anyway, so there's no need to check.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_extensions.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index ab27d43ca83..2d5b6c64614 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -42,6 +42,10 @@ static bool can_do_pipelined_register_writes(struct brw_context *brw) { + /* Supposedly, Broadwell just works. */ + if (brw->gen >= 8) + return true; + /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the * statistics registers), and we already reset it to zero before using it. */ @@ -50,7 +54,7 @@ can_do_pipelined_register_writes(struct brw_context *brw) const int offset = 100; /* The register we picked only exists on Gen7+. */ - assert(brw->gen >= 7); + assert(brw->gen == 7); uint32_t *data; /* Set a value in a BO to a known quantity. The workaround BO already |