diff options
| author | Samuel Pitoiset <[email protected]> | 2018-11-08 11:16:45 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-11-08 11:20:03 +0100 |
| commit | c472ad82e48e139e03ed28a7a98481814260d08e (patch) | |
| tree | 78b80276779761af28d71efd4a1996414c602b49 /src | |
| parent | f425d9ee74ce81be3aa9dfefad572d40c5d42372 (diff) | |
radv: fix GPU hangs when loading depth/stencil clear values on SI/CIK
HTILE is supported on these chips, not sure how I missed that.
This restores using PFP_SYNC_ME when LOAD_CONTEXT_REG is not used.
Fixes: f425d9ee74 ("radv: use LOAD_CONTEXT_REG when loading fast clear values")
Signed-off-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 24 |
1 files changed, 19 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 9fd9e81b3c1..ee5373950f6 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1317,11 +1317,25 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset; - radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0)); - radeon_emit(cs, va); - radeon_emit(cs, va >> 32); - radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START); - radeon_emit(cs, reg_count); + if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) { + radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0)); + radeon_emit(cs, va); + radeon_emit(cs, va >> 32); + radeon_emit(cs, (reg >> 2) - CONTEXT_SPACE_START); + radeon_emit(cs, reg_count); + } else { + radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0)); + radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) | + COPY_DATA_DST_SEL(COPY_DATA_REG) | + (reg_count == 2 ? COPY_DATA_COUNT_SEL : 0)); + radeon_emit(cs, va); + radeon_emit(cs, va >> 32); + radeon_emit(cs, reg >> 2); + radeon_emit(cs, 0); + + radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); + radeon_emit(cs, 0); + } } /* |