diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2016-12-17 13:27:37 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2016-12-18 20:52:37 +0100 |
| commit | bfee9866ea87fb0a81b3165f968ac45a4f5a25c3 (patch) | |
| tree | 49a09bfa3c22b27d9c2ba03fa3d4c97e1259850e /src | |
| parent | 9b0efc98ba00467681a72107f1f2eb9025536540 (diff) | |
radv: Use RELEASE_MEM packet for MEC timestamp query.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/common/sid.h | 1 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_query.c | 29 |
2 files changed, 21 insertions, 9 deletions
diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index 3b3983fe277..0a2c616e647 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -156,6 +156,7 @@ * DST_SEL=MC. Only CIK chips are affected. */ /*#define PKT3_EVENT_WRITE_EOS 0x48*/ /* fix CP DMA before uncommenting */ +#define PKT3_RELEASE_MEM 0x49 #define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */ #define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */ #define PKT3_SET_CONFIG_REG 0x68 diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index 185968689ac..06762dee086 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -387,6 +387,7 @@ void radv_CmdWriteTimestamp( { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_query_pool, pool, queryPool); + bool mec = radv_cmd_buffer_uses_mec(cmd_buffer); struct radeon_winsys_cs *cs = cmd_buffer->cs; uint64_t va = cmd_buffer->device->ws->buffer_get_va(pool->bo); uint64_t avail_va = va + pool->availability_offset + 4 * query; @@ -394,17 +395,27 @@ void radv_CmdWriteTimestamp( cmd_buffer->device->ws->cs_add_buffer(cs, pool->bo, 5); - MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 11); - - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5)); - radeon_emit(cs, query_va); - radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF)); - radeon_emit(cs, 0); - radeon_emit(cs, 0); + MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 12); + + if (mec) { + radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5)); + radeon_emit(cs, 3 << 29); + radeon_emit(cs, query_va); + radeon_emit(cs, query_va >> 32); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + } else { + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_BOTTOM_OF_PIPE_TS) | EVENT_INDEX(5)); + radeon_emit(cs, query_va); + radeon_emit(cs, (3 << 29) | ((query_va >> 32) & 0xFFFF)); + radeon_emit(cs, 0); + radeon_emit(cs, 0); + } radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); - radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) | + radeon_emit(cs, S_370_DST_SEL(mec ? V_370_MEM_ASYNC : V_370_MEMORY_SYNC) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_ME)); radeon_emit(cs, avail_va); |