diff options
| author | Tom Stellard <[email protected]> | 2012-08-01 16:20:20 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-14 14:06:20 +0000 |
| commit | b49771970bb8d06a179da69a7eb6b0af1b379d2d (patch) | |
| tree | 1a9c9fb29ab42b5729bace69670f4a392df87fdd /src | |
| parent | 2fae8227ad906a6d6290134368b62f5dd3a1858e (diff) | |
radeon/llvm: Inline immediate offset when lowering implicit parameters
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/R600ISelLowering.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index 4d8c928f49b..7f79359fb21 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -254,18 +254,22 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBlock &BB, MachineRegisterInfo & MRI, unsigned dword_offset) const { + unsigned ByteOffset = dword_offset * 4; + + // We shouldn't be using an offset wider than 16-bits for implicit parameters. + assert(isInt<16>(ByteOffset)); + MachineBasicBlock::iterator I = *MI; unsigned PtrReg = MRI.createVirtualRegister(&AMDGPU::R600_TReg32_XRegClass); MRI.setRegClass(MI->getOperand(0).getReg(), &AMDGPU::R600_TReg32_XRegClass); - BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::MOV), PtrReg) - .addReg(AMDGPU::ALU_LITERAL_X) - .addImm(dword_offset * 4); + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::COPY), PtrReg) + .addReg(AMDGPU::ZERO); BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_i32_eg)) .addOperand(MI->getOperand(0)) .addReg(PtrReg) - .addImm(0); + .addImm(ByteOffset); } //===----------------------------------------------------------------------===// |