diff options
| author | Francisco Jerez <[email protected]> | 2016-09-01 22:39:00 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-09-14 14:50:59 -0700 |
| commit | 5ca35c63673dad28854c00ce34ec6f085ba4ec5e (patch) | |
| tree | 085a0f67b488e8d1632a852a773e02bb036b949a /src | |
| parent | f33a8f8fcfb6ce3baa8813b32d5eff20506f3df1 (diff) | |
i965/vec4: Assert that ATTR regions are register-aligned.
It might be useful to actually handle this once copy propagation
becomes smarter about register-misaligned offsets.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 470f814f562..58c8a8a5bdb 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -1620,6 +1620,7 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map, int grf = attribute_map[inst->src[i].nr + inst->src[i].offset / REG_SIZE]; + assert(inst->src[i].offset % REG_SIZE == 0); /* All attributes used in the shader need to have been assigned a * hardware register by the caller |