diff options
| author | Chad Versace <[email protected]> | 2013-07-18 10:07:30 -0700 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2013-07-18 16:18:22 -0700 |
| commit | 30f33deccb7d481f638e34f2d9d9c107df871eab (patch) | |
| tree | b3d95b9a395851f524b656c1cc2c81f20194685b /src | |
| parent | 2273b652bb884a6188af7f8d063d0d0fc5497054 (diff) | |
i965/hsw: Change L3 MOCS for depth, hiz, and stencil
Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.
Reviewed-by: Kenneth Graunke <[email protected]>
Signed-off-by: Chad Versace <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_misc_state.c | 7 |
2 files changed, 9 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 0fa352aebfe..71a5a308e77 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -662,6 +662,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, uint32_t draw_x = params->depth.x_offset; uint32_t draw_y = params->depth.y_offset; uint32_t tile_mask_x, tile_mask_y; + uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; brw_get_depthstencil_tile_masks(params->depth.mt, params->depth.level, @@ -713,7 +714,7 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, offset); OUT_BATCH((params->depth.width + tile_x - 1) << 4 | (params->depth.height + tile_y - 1) << 18); - OUT_BATCH(0); + OUT_BATCH(mocs); OUT_BATCH(tile_x | tile_y << 16); OUT_BATCH(0); @@ -730,7 +731,8 @@ gen7_blorp_emit_depth_stencil_config(struct brw_context *brw, BEGIN_BATCH(3); OUT_BATCH((GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); - OUT_BATCH(hiz_region->pitch - 1); + OUT_BATCH((mocs << 25) | + (hiz_region->pitch - 1)); OUT_RELOC(hiz_region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, hiz_offset); diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 7f6188103dd..7d63b2e778b 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -40,6 +40,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, uint32_t tile_x, uint32_t tile_y) { struct gl_context *ctx = &brw->ctx; + uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; intel_emit_depth_stall_flushes(brw); @@ -63,7 +64,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, OUT_BATCH(((width + tile_x - 1) << 4) | ((height + tile_y - 1) << 18)); - OUT_BATCH(0); + OUT_BATCH(mocs); OUT_BATCH(tile_x | (tile_y << 16)); OUT_BATCH(0); ADVANCE_BATCH(); @@ -78,7 +79,8 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, struct intel_mipmap_tree *hiz_mt = depth_mt->hiz_mt; BEGIN_BATCH(3); OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); - OUT_BATCH(hiz_mt->region->pitch - 1); + OUT_BATCH((mocs << 25) | + (hiz_mt->region->pitch - 1)); OUT_RELOC(hiz_mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, @@ -108,6 +110,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw, * same text, and experiments indicate that this is necessary. */ OUT_BATCH(enabled | + mocs << 25 | (2 * stencil_mt->region->pitch - 1)); OUT_RELOC(stencil_mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, |