diff options
| author | Kenneth Graunke <[email protected]> | 2014-08-11 08:13:05 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-08-12 13:39:25 -0700 |
| commit | 17c17b87f9be5403f706f491756de1be26376308 (patch) | |
| tree | f2d5937983b64bd802fcc330258f007cda83b185 /src | |
| parent | af13cf609f4257768ad8b80be8cec7f2e6ca8c81 (diff) | |
i965/vec4: Switch to MOV, not OR, for GS_OPCODE_THREAD_END on Gen8.
Either should work.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp index bf904c674e2..cbac89d6f78 100644 --- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp +++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp @@ -202,10 +202,9 @@ gen8_vec4_generator::generate_gs_thread_end(vec4_instruction *ir) /* Enable Channel Masks in the URB_WRITE_HWORD message header */ default_state.access_mode = BRW_ALIGN_1; - inst = OR(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5), - BRW_REGISTER_TYPE_UD), - retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD), - brw_imm_ud(0xff00)); /* could be 0x1100 but shouldn't matter */ + inst = MOV(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5), + BRW_REGISTER_TYPE_UD), + brw_imm_ud(0xff00)); /* could be 0x1100 but shouldn't matter */ gen8_set_mask_control(inst, BRW_MASK_DISABLE); default_state.access_mode = BRW_ALIGN_16; |