diff options
| author | Eric Anholt <[email protected]> | 2019-02-26 09:05:05 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2019-03-05 12:57:39 -0800 |
| commit | dff1fc04e0be93ff45744d2d75d8b643cf59ecfc (patch) | |
| tree | c4164038ed0ca7a1eabd8237531077212e7e1121 /src | |
| parent | 4739181a160cd941f7af78074c4f4ac7c6a1fd76 (diff) | |
v3d: Add support for vir-to-qpu of ldunif instructions to a temp.
We can load a uniform to any register, so add support for non-ALU
instructions with sig.ldunif to a temp.
Diffstat (limited to 'src')
| -rw-r--r-- | src/broadcom/compiler/vir_to_qpu.c | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/src/broadcom/compiler/vir_to_qpu.c b/src/broadcom/compiler/vir_to_qpu.c index c82c1aae6e6..cc499d8ba09 100644 --- a/src/broadcom/compiler/vir_to_qpu.c +++ b/src/broadcom/compiler/vir_to_qpu.c @@ -309,7 +309,20 @@ v3d_generate_code_block(struct v3d_compile *c, } if (qinst->qpu.type == V3D_QPU_INSTR_TYPE_ALU) { - if (v3d_qpu_sig_writes_address(c->devinfo, + if (qinst->qpu.sig.ldunif) { + assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP); + assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP); + + if (!dst.magic || + dst.index != V3D_QPU_WADDR_R5) { + assert(c->devinfo->ver >= 40); + + qinst->qpu.sig.ldunif = false; + qinst->qpu.sig.ldunifrf = true; + qinst->qpu.sig_addr = dst.index; + qinst->qpu.sig_magic = dst.magic; + } + } else if (v3d_qpu_sig_writes_address(c->devinfo, &qinst->qpu.sig)) { assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP); assert(qinst->qpu.alu.mul.op == V3D_QPU_M_NOP); @@ -361,7 +374,7 @@ reads_uniform(const struct v3d_device_info *devinfo, uint64_t instruction) assert(ok); if (qpu.sig.ldunif || - qpu.sig.ldunifarf || + qpu.sig.ldunifrf || qpu.sig.wrtmuc) { return true; } |