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authorNicolai Hähnle <[email protected]>2016-03-14 10:22:21 -0500
committerNicolai Hähnle <[email protected]>2016-03-21 15:34:25 -0500
commit97352aa50af87b50271bc632abfb971caca46e2b (patch)
tree8b21ef885f2fcbb871c720d7e1ed86a3bc1149fe /src
parent5a61b428f477e7eef9f18f2fd43f661f193ece39 (diff)
radeonsi: implement volatile memory access
Prevent loads from being re-ordered or coalesced. Atomics don't need special handling by definition, and stores don't need special handling because LLVM is unable to detect dead image or buffer stores. Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeonsi/si_shader.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c
index db0cc5bbf62..0d26957101e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2915,6 +2915,7 @@ static void load_emit(
struct lp_build_tgsi_context *bld_base,
struct lp_build_emit_data *emit_data)
{
+ struct si_shader_context *ctx = si_shader_context(bld_base);
struct gallivm_state *gallivm = bld_base->base.gallivm;
LLVMBuilderRef builder = gallivm->builder;
const struct tgsi_full_instruction * inst = emit_data->inst;
@@ -2922,6 +2923,9 @@ static void load_emit(
char intrinsic_name[32];
char coords_type[8];
+ if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
+ emit_optimization_barrier(ctx);
+
if (target == TGSI_TEXTURE_BUFFER) {
emit_data->output[emit_data->chan] = lp_build_intrinsic(
builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,