diff options
| author | Kenneth Graunke <[email protected]> | 2013-06-13 14:55:18 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-06-26 11:25:12 -0700 |
| commit | 9321f3257f0199c5988fd2e220874acd8b7f0a53 (patch) | |
| tree | eb0444580908706ce19622a674983d10cd664b0f /src | |
| parent | 4563dfe23a300f0fc1652a609f5ad9e9a755fb99 (diff) | |
i965: Add back strict type assertions for MAD and LRP.
Commit 526ffdfc033ab01cf133cb7e8290c65d12ccc9be relaxed the type
assertions in brw_alu3 to allow D/UD types (required by BFE and BFI2).
This lost us the strict type checking for MAD and LRP, which require
all four types to be float.
This patch adds a new ALU3F wrapper which checks these once again.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index 31d97ca5c28..3d0db1b03d3 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -905,6 +905,20 @@ struct brw_instruction *brw_##OP(struct brw_compile *p, \ return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \ } +#define ALU3F(OP) \ +struct brw_instruction *brw_##OP(struct brw_compile *p, \ + struct brw_reg dest, \ + struct brw_reg src0, \ + struct brw_reg src1, \ + struct brw_reg src2) \ +{ \ + assert(dest.type == BRW_REGISTER_TYPE_F); \ + assert(src0.type == BRW_REGISTER_TYPE_F); \ + assert(src1.type == BRW_REGISTER_TYPE_F); \ + assert(src2.type == BRW_REGISTER_TYPE_F); \ + return brw_alu3(p, BRW_OPCODE_##OP, dest, src0, src1, src2); \ +} + /* Rounding operations (other than RNDD) require two instructions - the first * stores a rounded value (possibly the wrong way) in the dest register, but * also sets a per-channel "increment bit" in the flag register. A predicated @@ -955,8 +969,8 @@ ALU2(DP3) ALU2(DP2) ALU2(LINE) ALU2(PLN) -ALU3(MAD) -ALU3(LRP) +ALU3F(MAD) +ALU3F(LRP) ALU1(BFREV) ALU3(BFE) ALU2(BFI1) |