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authorMatt Turner <[email protected]>2013-09-19 22:55:24 -0700
committerMatt Turner <[email protected]>2013-10-07 10:43:19 -0700
commit69909c866b6595f80d206c8e2484b1dc6668e7be (patch)
treecfb1fb3386c5104e4bf35185ac6238a1ab50b4ea /src
parent92dc16c3e2e2b9e3e71baaccc67bbe727e9d68ab (diff)
i965: Add Gen assertion checks for newer instructions.
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_generator.cpp11
-rw-r--r--src/mesa/drivers/dri/i965/brw_vec4_generator.cpp11
2 files changed, 22 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8fe42033481..a35c172c81c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1244,6 +1244,7 @@ fs_generator::generate_code(exec_list *instructions)
break;
case BRW_OPCODE_MAD:
+ assert(brw->gen >= 6);
brw_set_access_mode(p, BRW_ALIGN_16);
if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
@@ -1258,6 +1259,7 @@ fs_generator::generate_code(exec_list *instructions)
break;
case BRW_OPCODE_LRP:
+ assert(brw->gen >= 6);
brw_set_access_mode(p, BRW_ALIGN_16);
if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
@@ -1306,9 +1308,11 @@ fs_generator::generate_code(exec_list *instructions)
brw_SHL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_F32TO16:
+ assert(brw->gen >= 7);
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
+ assert(brw->gen >= 7);
brw_F16TO32(p, dst, src[0]);
break;
case BRW_OPCODE_CMP:
@@ -1318,19 +1322,23 @@ fs_generator::generate_code(exec_list *instructions)
brw_SEL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_BFREV:
+ assert(brw->gen >= 7);
/* BFREV only supports UD type for src and dst. */
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_FBH:
+ assert(brw->gen >= 7);
/* FBH only supports UD type for dst. */
brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_FBL:
+ assert(brw->gen >= 7);
/* FBL only supports UD type for dst. */
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_CBIT:
+ assert(brw->gen >= 7);
/* CBIT only supports UD type for dst. */
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
@@ -1348,6 +1356,7 @@ fs_generator::generate_code(exec_list *instructions)
break;
case BRW_OPCODE_BFE:
+ assert(brw->gen >= 7);
brw_set_access_mode(p, BRW_ALIGN_16);
if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
@@ -1362,9 +1371,11 @@ fs_generator::generate_code(exec_list *instructions)
break;
case BRW_OPCODE_BFI1:
+ assert(brw->gen >= 7);
brw_BFI1(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_BFI2:
+ assert(brw->gen >= 7);
brw_set_access_mode(p, BRW_ALIGN_16);
if (dispatch_width == 16) {
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index ae6e43ca34a..67af0ddec8d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -873,6 +873,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
break;
case BRW_OPCODE_MAD:
+ assert(brw->gen >= 6);
brw_MAD(p, dst, src[0], src[1], src[2]);
break;
@@ -935,31 +936,38 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
break;
case BRW_OPCODE_F32TO16:
+ assert(brw->gen >= 7);
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
+ assert(brw->gen >= 7);
brw_F16TO32(p, dst, src[0]);
break;
case BRW_OPCODE_LRP:
+ assert(brw->gen >= 6);
brw_LRP(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_BFREV:
+ assert(brw->gen >= 7);
/* BFREV only supports UD type for src and dst. */
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_FBH:
+ assert(brw->gen >= 7);
/* FBH only supports UD type for dst. */
brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_FBL:
+ assert(brw->gen >= 7);
/* FBL only supports UD type for dst. */
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_CBIT:
+ assert(brw->gen >= 7);
/* CBIT only supports UD type for dst. */
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
@@ -977,13 +985,16 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
break;
case BRW_OPCODE_BFE:
+ assert(brw->gen >= 7);
brw_BFE(p, dst, src[0], src[1], src[2]);
break;
case BRW_OPCODE_BFI1:
+ assert(brw->gen >= 7);
brw_BFI1(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_BFI2:
+ assert(brw->gen >= 7);
brw_BFI2(p, dst, src[0], src[1], src[2]);
break;