diff options
| author | Lionel Landwerlin <[email protected]> | 2018-09-07 11:55:45 +0100 |
|---|---|---|
| committer | Lionel Landwerlin <[email protected]> | 2018-09-07 14:46:20 +0100 |
| commit | 69874e9a6a61d1af92e4d70adaefe1308582c3a1 (patch) | |
| tree | 786696a1f34f95232812f6eb8b1e6212fbe25bc5 /src | |
| parent | 97fcccb25ed5f55139c03ebc1c71742f0f25f683 (diff) | |
intel/genxml: turn SLM Enable bit into boolean
Signed-off-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/intel/genxml/gen10.xml | 2 | ||||
| -rw-r--r-- | src/intel/genxml/gen8.xml | 2 | ||||
| -rw-r--r-- | src/intel/genxml/gen9.xml | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 541e4405716..abd5da297d6 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -3546,7 +3546,7 @@ </register> <register name="L3CNTLREG" length="1" num="0x7034"> - <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="SLM Enable" start="0" end="0" type="bool"/> <field name="URB Allocation" start="1" end="7" type="uint"/> <field name="RO Allocation" start="11" end="17" type="uint"/> <field name="DC Allocation" start="18" end="24" type="uint"/> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 330366b7ed0..d42c63aabd8 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -3199,7 +3199,7 @@ </register> <register name="L3CNTLREG" length="1" num="0x7034"> - <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="SLM Enable" start="0" end="0" type="bool"/> <field name="URB Allocation" start="1" end="7" type="uint"/> <field name="RO Allocation" start="11" end="17" type="uint"/> <field name="DC Allocation" start="18" end="24" type="uint"/> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 318ae89d5e7..ca268254503 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -3484,7 +3484,7 @@ </register> <register name="L3CNTLREG" length="1" num="0x7034"> - <field name="SLM Enable" start="0" end="0" type="uint"/> + <field name="SLM Enable" start="0" end="0" type="bool"/> <field name="URB Allocation" start="1" end="7" type="uint"/> <field name="RO Allocation" start="11" end="17" type="uint"/> <field name="DC Allocation" start="18" end="24" type="uint"/> |