diff options
| author | Marek Olšák <[email protected]> | 2017-08-24 23:46:46 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-08-28 21:45:33 +0200 |
| commit | 39205f216e5912df5f6ae9c4ded1a812a19929dd (patch) | |
| tree | c7e751d306304c3dcecdaa77d9503932a6ac2477 /src | |
| parent | 61187c1689bcd0498644705a8deaf6d0244866f3 (diff) | |
gallium/radeon: set EVENT_WRITE_EOP.INT_SEL = wait for write confirmation
Ported from Vulkan.
Not sure what this is good for.. maybe write confirmation from L2 flushes?
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/amd/common/r600d_common.h | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/r600_pipe_common.c | 12 |
2 files changed, 12 insertions, 3 deletions
diff --git a/src/amd/common/r600d_common.h b/src/amd/common/r600d_common.h index 57757469e52..76c5c4f5f9b 100644 --- a/src/amd/common/r600d_common.h +++ b/src/amd/common/r600d_common.h @@ -67,6 +67,9 @@ #define COPY_DATA_WR_CONFIRM (1 << 20) #define PKT3_EVENT_WRITE 0x46 #define PKT3_EVENT_WRITE_EOP 0x47 +#define EOP_INT_SEL(x) ((x) << 24) +#define EOP_INT_SEL_NONE 0 +#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3 #define EOP_DATA_SEL(x) ((x) << 29) #define EOP_DATA_SEL_DISCARD 0 #define EOP_DATA_SEL_VALUE_32BIT 1 diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index 7226fc21a04..7c12565d162 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -109,6 +109,12 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx, unsigned op = EVENT_TYPE(event) | EVENT_INDEX(5) | event_flags; + unsigned sel = EOP_DATA_SEL(data_sel); + + /* Wait for write confirmation before writing data, but don't send + * an interrupt. */ + if (ctx->chip_class >= SI && data_sel != EOP_DATA_SEL_DISCARD) + sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM); if (ctx->chip_class >= GFX9) { /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion @@ -136,7 +142,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx, radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0)); radeon_emit(cs, op); - radeon_emit(cs, EOP_DATA_SEL(data_sel)); + radeon_emit(cs, sel); radeon_emit(cs, va); /* address lo */ radeon_emit(cs, va >> 32); /* address hi */ radeon_emit(cs, new_fence); /* immediate data lo */ @@ -155,7 +161,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx, radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); radeon_emit(cs, op); radeon_emit(cs, va); - radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel)); + radeon_emit(cs, ((va >> 32) & 0xffff) | sel); radeon_emit(cs, 0); /* immediate data */ radeon_emit(cs, 0); /* unused */ @@ -166,7 +172,7 @@ void r600_gfx_write_event_eop(struct r600_common_context *ctx, radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0)); radeon_emit(cs, op); radeon_emit(cs, va); - radeon_emit(cs, ((va >> 32) & 0xffff) | EOP_DATA_SEL(data_sel)); + radeon_emit(cs, ((va >> 32) & 0xffff) | sel); radeon_emit(cs, new_fence); /* immediate data */ radeon_emit(cs, 0); /* unused */ } |