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authorSamuel Pitoiset <[email protected]>2018-03-26 11:28:48 +0200
committerSamuel Pitoiset <[email protected]>2018-03-30 17:32:15 +0200
commit2a329f4ada27d22e8fdb9cd6924d1da7364c3336 (patch)
treecafffee8d64f9fc3995104021e58ec74eb164610 /src
parentfc1d1dbe81e16041ec0d84811d171f7d42975eea (diff)
radv: set SAMPLE_RATE to the number of samples of the current fb
Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c7
-rw-r--r--src/amd/vulkan/radv_pass.c12
-rw-r--r--src/amd/vulkan/radv_private.h1
3 files changed, 16 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index cadb06f0af5..f0a0b086781 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1180,15 +1180,18 @@ void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
}
} else {
+ const struct radv_subpass *subpass = cmd_buffer->state.subpass;
+ uint32_t sample_rate = subpass ? util_logbase2(subpass->max_sample_count) : 0;
+
if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) {
db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(0) | /* TODO: set this to the number of samples of the current framebuffer */
+ S_028004_SAMPLE_RATE(sample_rate) |
S_028004_ZPASS_ENABLE(1) |
S_028004_SLICE_EVEN_ENABLE(1) |
S_028004_SLICE_ODD_ENABLE(1);
} else {
db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
- S_028004_SAMPLE_RATE(0); /* TODO: set this to the number of samples of the current framebuffer */
+ S_028004_SAMPLE_RATE(sample_rate);
}
}
diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
index 30289557164..d059af54f9b 100644
--- a/src/amd/vulkan/radv_pass.c
+++ b/src/amd/vulkan/radv_pass.c
@@ -106,6 +106,7 @@ VkResult radv_CreateRenderPass(
p = pass->subpass_attachments;
for (uint32_t i = 0; i < pCreateInfo->subpassCount; i++) {
const VkSubpassDescription *desc = &pCreateInfo->pSubpasses[i];
+ uint32_t color_sample_count = 1, depth_sample_count = 1;
struct radv_subpass *subpass = &pass->subpasses[i];
subpass->input_count = desc->inputAttachmentCount;
@@ -132,8 +133,10 @@ VkResult radv_CreateRenderPass(
for (uint32_t j = 0; j < desc->colorAttachmentCount; j++) {
subpass->color_attachments[j]
= desc->pColorAttachments[j];
- if (desc->pColorAttachments[j].attachment != VK_ATTACHMENT_UNUSED)
+ if (desc->pColorAttachments[j].attachment != VK_ATTACHMENT_UNUSED) {
pass->attachments[desc->pColorAttachments[j].attachment].view_mask |= subpass->view_mask;
+ color_sample_count = pCreateInfo->pAttachments[desc->pColorAttachments[j].attachment].samples;
+ }
}
}
@@ -156,11 +159,16 @@ VkResult radv_CreateRenderPass(
if (desc->pDepthStencilAttachment) {
subpass->depth_stencil_attachment =
*desc->pDepthStencilAttachment;
- if (desc->pDepthStencilAttachment->attachment != VK_ATTACHMENT_UNUSED)
+ if (desc->pDepthStencilAttachment->attachment != VK_ATTACHMENT_UNUSED) {
pass->attachments[desc->pDepthStencilAttachment->attachment].view_mask |= subpass->view_mask;
+ depth_sample_count = pCreateInfo->pAttachments[desc->pDepthStencilAttachment->attachment].samples;
+ }
} else {
subpass->depth_stencil_attachment.attachment = VK_ATTACHMENT_UNUSED;
}
+
+ subpass->max_sample_count = MAX2(color_sample_count,
+ depth_sample_count);
}
for (unsigned i = 0; i < pCreateInfo->dependencyCount; ++i) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index ce2e487bdb5..a5cbad6cfe0 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1586,6 +1586,7 @@ struct radv_subpass {
struct radv_subpass_barrier start_barrier;
uint32_t view_mask;
+ VkSampleCountFlagBits max_sample_count;
};
struct radv_render_pass_attachment {