diff options
| author | Marek Olšák <[email protected]> | 2016-02-24 01:24:06 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-03-09 15:02:26 +0100 |
| commit | f4aa3256ef2965d558b646b32d5e59280db7021d (patch) | |
| tree | b5a635afe197658fc5f4a754aaf58e0bbcac416f /src | |
| parent | bd1feb28273e8d7047304e5a2a02ca3d71de5533 (diff) | |
winsys/amdgpu: allow drivers to set/get opaque metadata
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_winsys.h | 10 | ||||
| -rw-r--r-- | src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 566322c60ab..5ca2414ef64 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -278,6 +278,9 @@ struct radeon_info { /* Tiling info for display code, DRI sharing, and other data. */ struct radeon_bo_metadata { + /* Tiling flags describing the texture layout for display code + * and DRI sharing. + */ enum radeon_bo_layout microtile; enum radeon_bo_layout macrotile; unsigned pipe_config; @@ -289,6 +292,13 @@ struct radeon_bo_metadata { unsigned num_banks; unsigned stride; bool scanout; + + /* Additional metadata associated with the buffer, in bytes. + * The maximum size is 64 * 4. This is opaque for the winsys & kernel. + * Supported by amdgpu only. + */ + uint32_t size_metadata; + uint32_t metadata[64]; }; enum radeon_feature_id { diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index 10ac2b25c6b..b670f263329 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -417,6 +417,9 @@ static void amdgpu_buffer_get_metadata(struct pb_buffer *_buf, md->tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT)); md->mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); md->scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /* DISPLAY */ + + md->size_metadata = info.metadata.size_metadata; + memcpy(md->metadata, info.metadata.umd_metadata, sizeof(md->metadata)); } static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf, @@ -447,6 +450,8 @@ static void amdgpu_buffer_set_metadata(struct pb_buffer *_buf, tiling_flags |= AMDGPU_TILING_SET(MICRO_TILE_MODE, 1); /* THIN_MICRO_TILING */ metadata.tiling_info = tiling_flags; + metadata.size_metadata = md->size_metadata; + memcpy(metadata.umd_metadata, md->metadata, sizeof(md->metadata)); amdgpu_bo_set_metadata(bo->bo, &metadata); } |