radeonsi: remove redundant si_texture offset and size fields

Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>

7 files changed, 106 insertions, 123 deletions

diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 68ed4cc5002..f5d7e2eb6ea 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -453,7 +453,7 @@ static void si_blit_decompress_color(struct si_context *sctx,
 	if (need_dcc_decompress) {
 		custom_blend = sctx->custom_blend_dcc_decompress;
 
-		assert(tex->dcc_offset);
+		assert(tex->surface.dcc_offset);
 
 		/* disable levels without DCC */
 		for (int i = first_level; i <= last_level; i++) {
@@ -519,7 +519,7 @@ si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
 			    unsigned first_level, unsigned last_level)
 {
 	/* CMASK or DCC can be discarded and we can still end up here. */
-	if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->dcc_offset)
+	if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->surface.dcc_offset)
 		return;
 
 	si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
@@ -582,7 +582,7 @@ static void si_check_render_feedback_texture(struct si_context *sctx,
 {
 	bool render_feedback = false;
 
-	if (!tex->dcc_offset)
+	if (!tex->surface.dcc_offset)
 		return;
 
 	for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
@@ -840,7 +840,7 @@ static void si_decompress_subresource(struct pipe_context *ctx,
 		si_decompress_depth(sctx, stex, planes,
 				    level, level,
 				    first_layer, last_layer);
-	} else if (stex->surface.fmask_size || stex->cmask_buffer || stex->dcc_offset) {
+	} else if (stex->surface.fmask_size || stex->cmask_buffer || stex->surface.dcc_offset) {
 		/* If we've rendered into the framebuffer and it's a blitting
 		 * source, make sure the decompression pass is invoked
 		 * by dirtying the framebuffer.
@@ -896,7 +896,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
 	    !util_format_is_compressed(dst->format) &&
 	    !util_format_is_depth_or_stencil(src->format) &&
 	    src->nr_samples <= 1 &&
-	    !sdst->dcc_offset &&
+	    !sdst->surface.dcc_offset &&
 	    !(dst->target != src->target &&
 	      (src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
 		si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz, src_box);
@@ -1288,12 +1288,12 @@ static void si_flush_resource(struct pipe_context *ctx,
 	if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
 		return;
 
-	if (!tex->is_depth && (tex->cmask_buffer || tex->dcc_offset)) {
+	if (!tex->is_depth && (tex->cmask_buffer || tex->surface.dcc_offset)) {
 		si_blit_decompress_color(sctx, tex, 0, res->last_level,
 					 0, util_max_layer(res, 0),
 					 tex->dcc_separate_buffer != NULL);
 
-		if (tex->display_dcc_offset)
+		if (tex->surface.display_dcc_offset)
 			si_retile_dcc(sctx, tex);
 	}
 
@@ -1333,7 +1333,7 @@ void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
 	/* If graphics is disabled, we can't decompress DCC, but it shouldn't
 	 * be compressed either. The caller should simply discard it.
 	 */
-	if (!tex->dcc_offset || !sctx->has_graphics)
+	if (!tex->surface.dcc_offset || !sctx->has_graphics)
 		return;
 
 	si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index 34a39a0edae..68a0eeb36b4 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -245,7 +245,7 @@ bool vi_dcc_clear_level(struct si_context *sctx,
 		dcc_offset = 0;
 	} else {
 		dcc_buffer = &tex->buffer.b.b;
-		dcc_offset = tex->dcc_offset;
+		dcc_offset = tex->surface.dcc_offset;
 	}
 
 	if (sctx->chip_class >= GFX9) {
@@ -515,7 +515,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 			if (tex->buffer.b.b.nr_samples >= 2 && tex->cmask_buffer) {
 				uint32_t clear_value = 0xCCCCCCCC;
 				si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
-						tex->cmask_offset, tex->surface.cmask_size,
+						tex->surface.cmask_offset, tex->surface.cmask_size,
 						&clear_value, 4, SI_COHERENCY_CB_META, false);
 				fmask_decompress_needed = true;
 			}
@@ -540,7 +540,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
 			/* Do the fast clear. */
 			uint32_t clear_value = 0;
 			si_clear_buffer(sctx, &tex->cmask_buffer->b.b,
-					tex->cmask_offset, tex->surface.cmask_size,
+					tex->surface.cmask_offset, tex->surface.cmask_size,
 					&clear_value, 4, SI_COHERENCY_CB_META, false);
 			eliminate_needed = true;
 		}
@@ -692,7 +692,7 @@ static void si_clear_render_target(struct pipe_context *ctx,
 	struct si_context *sctx = (struct si_context *)ctx;
 	struct si_texture *sdst = (struct si_texture*)dst->texture;
 
-	if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
+	if (dst->texture->nr_samples <= 1 && !sdst->surface.dcc_offset) {
 		si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width,
 					       height, render_condition_enabled);
 		return;
diff --git a/src/gallium/drivers/radeonsi/si_compute_blit.c b/src/gallium/drivers/radeonsi/si_compute_blit.c
index 3704debd60b..4b3d1df935c 100644
--- a/src/gallium/drivers/radeonsi/si_compute_blit.c
+++ b/src/gallium/drivers/radeonsi/si_compute_blit.c
@@ -451,9 +451,9 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
 	unsigned num_elements = tex->surface.u.gfx9.dcc_retile_num_elements;
 	struct pipe_image_view img[3];
 
-	assert(tex->dcc_retile_map_offset && tex->dcc_retile_map_offset <= UINT_MAX);
-	assert(tex->dcc_offset && tex->dcc_offset <= UINT_MAX);
-	assert(tex->display_dcc_offset && tex->display_dcc_offset <= UINT_MAX);
+	assert(tex->surface.dcc_retile_map_offset && tex->surface.dcc_retile_map_offset <= UINT_MAX);
+	assert(tex->surface.dcc_offset && tex->surface.dcc_offset <= UINT_MAX);
+	assert(tex->surface.display_dcc_offset && tex->surface.display_dcc_offset <= UINT_MAX);
 
 	for (unsigned i = 0; i < 3; i++) {
 		img[i].resource = &tex->buffer.b.b;
@@ -463,15 +463,15 @@ void si_retile_dcc(struct si_context *sctx, struct si_texture *tex)
 
 	img[0].format = use_uint16 ? PIPE_FORMAT_R16G16B16A16_UINT :
 				     PIPE_FORMAT_R32G32B32A32_UINT;
-	img[0].u.buf.offset = tex->dcc_retile_map_offset;
+	img[0].u.buf.offset = tex->surface.dcc_retile_map_offset;
 	img[0].u.buf.size = num_elements * (use_uint16 ? 2 : 4);
 
 	img[1].format = PIPE_FORMAT_R8_UINT;
-	img[1].u.buf.offset = tex->dcc_offset;
+	img[1].u.buf.offset = tex->surface.dcc_offset;
 	img[1].u.buf.size = tex->surface.dcc_size;
 
 	img[2].format = PIPE_FORMAT_R8_UINT;
-	img[2].u.buf.offset = tex->display_dcc_offset;
+	img[2].u.buf.offset = tex->surface.display_dcc_offset;
 	img[2].u.buf.size = tex->surface.u.gfx9.display_dcc_size;
 
 	ctx->set_shader_images(ctx, PIPE_SHADER_COMPUTE, 0, 3, img);
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 38b9b11a83c..a5769df28cb 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -344,7 +344,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 
 		if (vi_dcc_enabled(tex, first_level)) {
 			meta_va = (!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
-				  tex->dcc_offset;
+				  tex->surface.dcc_offset;
 
 			if (sscreen->info.chip_class == GFX8) {
 				meta_va += base_level_info->dcc_offset;
@@ -356,7 +356,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 			meta_va |= dcc_tile_swizzle;
 		} else if (vi_tc_compat_htile_enabled(tex, first_level,
 						      is_stencil ? PIPE_MASK_S : PIPE_MASK_Z)) {
-			meta_va = tex->buffer.gpu_address + tex->htile_offset;
+			meta_va = tex->buffer.gpu_address + tex->surface.htile_offset;
 		}
 
 		if (meta_va)
@@ -381,7 +381,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 		if (meta_va) {
 			struct gfx9_surf_meta_flags meta;
 
-			if (tex->dcc_offset)
+			if (tex->surface.dcc_offset)
 				meta = tex->surface.u.gfx9.dcc;
 			else
 				meta = tex->surface.u.gfx9.htile;
@@ -409,7 +409,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
 		if (meta_va) {
 			struct gfx9_surf_meta_flags meta;
 
-			if (tex->dcc_offset)
+			if (tex->surface.dcc_offset)
 				meta = tex->surface.u.gfx9.dcc;
 			else
 				meta = tex->surface.u.gfx9.htile;
@@ -498,7 +498,7 @@ static bool color_needs_decompression(struct si_texture *tex)
 {
 	return tex->surface.fmask_size ||
 	       (tex->dirty_level_mask &&
-		(tex->cmask_buffer || tex->dcc_offset));
+		(tex->cmask_buffer || tex->surface.dcc_offset));
 }
 
 static bool depth_needs_decompression(struct si_texture *tex)
@@ -547,7 +547,7 @@ static void si_set_sampler_view(struct si_context *sctx,
 				samplers->needs_color_decompress_mask &= ~(1u << slot);
 			}
 
-			if (tex->dcc_offset &&
+			if (tex->surface.dcc_offset &&
 			    p_atomic_read(&tex->framebuffers_bound))
 				sctx->need_check_render_feedback = true;
 		}
@@ -2532,7 +2532,7 @@ static void si_make_texture_handle_resident(struct pipe_context *ctx,
 					tex_handle);
 			}
 
-			if (tex->dcc_offset &&
+			if (tex->surface.dcc_offset &&
 			    p_atomic_read(&tex->framebuffers_bound))
 				sctx->need_check_render_feedback = true;
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 86aee2e0824..2c3471de9ea 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -288,7 +288,6 @@ struct si_texture {
 	struct si_resource		buffer;
 
 	struct radeon_surf		surface;
-	uint64_t			size;
 	struct si_texture		*flushed_depth_texture;
 
 	/* One texture allocation can contain these buffers:
@@ -300,20 +299,14 @@ struct si_texture {
 	 * - displayable DCC buffer (if the DCC buffer is not displayable)
 	 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
 	 */
-	uint64_t			fmask_offset;
-	uint64_t			cmask_offset;
 	uint64_t			cmask_base_address_reg;
 	struct si_resource		*cmask_buffer;
-	uint64_t			dcc_offset; /* 0 = disabled */
-	uint64_t			display_dcc_offset;
-	uint64_t			dcc_retile_map_offset;
 	unsigned			cb_color_info; /* fast clear enable bit */
 	unsigned			color_clear_value[2];
 	unsigned			last_msaa_resolve_target_micro_mode;
 	unsigned			num_level0_transfers;
 
 	/* Depth buffer compression and fast clear. */
-	uint64_t			htile_offset;
 	float				depth_clear_value;
 	uint16_t			dirty_level_mask; /* each bit says if that mipmap is compressed */
 	uint16_t			stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
@@ -1550,7 +1543,7 @@ si_texture_reference(struct si_texture **ptr, struct si_texture *res)
 static inline bool
 vi_dcc_enabled(struct si_texture *tex, unsigned level)
 {
-	return tex->dcc_offset && level < tex->surface.num_dcc_levels;
+	return tex->surface.dcc_offset && level < tex->surface.num_dcc_levels;
 }
 
 static inline unsigned
@@ -1747,13 +1740,13 @@ si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
 	if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
 		return false;
 
-	return tex->htile_offset && level == 0;
+	return tex->surface.htile_offset && level == 0;
 }
 
 static inline bool
 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
 {
-	assert(!tex->tc_compatible_htile || tex->htile_offset);
+	assert(!tex->tc_compatible_htile || tex->surface.htile_offset);
 	return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 1d086b65fa4..893968d1997 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2535,7 +2535,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
 		color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
 				S_028C74_NUM_FRAGMENTS(log_fragments);
 
-		if (tex->fmask_offset) {
+		if (tex->surface.fmask_offset) {
 			color_info |= S_028C70_COMPRESSION(1);
 			unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
 
@@ -2703,7 +2703,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 			}
 
 			surf->db_htile_data_base = (tex->buffer.gpu_address +
-						    tex->htile_offset) >> 8;
+						    tex->surface.htile_offset) >> 8;
 			surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
 						 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
 			if (sctx->chip_class == GFX9) {
@@ -2784,7 +2784,7 @@ static void si_init_depth_surface(struct si_context *sctx,
 			}
 
 			surf->db_htile_data_base = (tex->buffer.gpu_address +
-						    tex->htile_offset) >> 8;
+						    tex->surface.htile_offset) >> 8;
 			surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
 
 			if (tex->tc_compatible_htile) {
@@ -2828,7 +2828,7 @@ void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
 		struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
 		struct si_texture *tex = (struct si_texture*)surf->texture;
 
-		if (tex->fmask_offset)
+		if (tex->surface.fmask_offset)
 			tex->dirty_level_mask |= 1 << surf->u.tex.level;
 		if (tex->dcc_gather_statistics)
 			tex->separate_dcc_dirty = true;
@@ -3013,7 +3013,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
 		if (surf->color_is_int10)
 			sctx->framebuffer.color_is_int10 |= 1 << i;
 
-		if (tex->fmask_offset)
+		if (tex->surface.fmask_offset)
 			sctx->framebuffer.compressed_cb_mask |= 1 << i;
 		else
 			sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
@@ -3206,8 +3206,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 		if (cb->base.u.tex.level > 0)
 			cb_color_info &= C_028C70_FAST_CLEAR;
 
-		if (tex->fmask_offset) {
-			cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
+		if (tex->surface.fmask_offset) {
+			cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
 			cb_color_fmask |= tex->surface.fmask_tile_swizzle;
 		}
 
@@ -3222,7 +3222,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 				cb_color_info |= S_028C70_DCC_ENABLE(1);
 
 			cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
-				       tex->dcc_offset) >> 8;
+				       tex->surface.dcc_offset) >> 8;
 
 			unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
 			dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
@@ -3235,7 +3235,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 			/* Set mutable surface parameters. */
 			cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
 			cb_color_base |= tex->surface.tile_swizzle;
-			if (!tex->fmask_offset)
+			if (!tex->surface.fmask_offset)
 				cb_color_fmask = cb_color_base;
 			if (cb->base.u.tex.level > 0)
 				cb_color_cmask = cb_color_base;
@@ -3277,7 +3277,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 		} else if (sctx->chip_class == GFX9) {
 			struct gfx9_surf_meta_flags meta;
 
-			if (tex->dcc_offset)
+			if (tex->surface.dcc_offset)
 				meta = tex->surface.u.gfx9.dcc;
 			else
 				meta = tex->surface.u.gfx9.cmask;
@@ -3285,7 +3285,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 			/* Set mutable surface parameters. */
 			cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
 			cb_color_base |= tex->surface.tile_swizzle;
-			if (!tex->fmask_offset)
+			if (!tex->surface.fmask_offset)
 				cb_color_fmask = cb_color_base;
 			if (cb->base.u.tex.level > 0)
 				cb_color_cmask = cb_color_base;
@@ -3325,7 +3325,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 			if (level_info->mode == RADEON_SURF_MODE_2D)
 				cb_color_base |= tex->surface.tile_swizzle;
 
-			if (!tex->fmask_offset)
+			if (!tex->surface.fmask_offset)
 				cb_color_fmask = cb_color_base;
 			if (cb->base.u.tex.level > 0)
 				cb_color_cmask = cb_color_base;
@@ -3341,7 +3341,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
 			cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
 			cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
 
-			if (tex->fmask_offset) {
+			if (tex->surface.fmask_offset) {
 				if (sctx->chip_class >= GFX7)
 					cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
 				cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
@@ -3996,17 +3996,17 @@ gfx10_make_texture_descriptor(struct si_screen *screen,
 	state[6] = 0;
 	state[7] = 0;
 
-	if (tex->dcc_offset) {
+	if (tex->surface.dcc_offset) {
 		state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
 			    S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
 			    S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
 	}
 
 	/* Initialize the sampler view for FMASK. */
-	if (tex->fmask_offset) {
+	if (tex->surface.fmask_offset) {
 		uint32_t format;
 
-		va = tex->buffer.gpu_address + tex->fmask_offset;
+		va = tex->buffer.gpu_address + tex->surface.fmask_offset;
 
 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
 		switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
@@ -4279,7 +4279,7 @@ si_make_texture_descriptor(struct si_screen *screen,
 		state[5] |= S_008F24_LAST_ARRAY(last_layer);
 	}
 
-	if (tex->dcc_offset) {
+	if (tex->surface.dcc_offset) {
 		state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
 	} else {
 		/* The last dword is unused by hw. The shader uses it to clear
@@ -4294,10 +4294,10 @@ si_make_texture_descriptor(struct si_screen *screen,
 	}
 
 	/* Initialize the sampler view for FMASK. */
-	if (tex->fmask_offset) {
+	if (tex->surface.fmask_offset) {
 		uint32_t data_format, num_format;
 
-		va = tex->buffer.gpu_address + tex->fmask_offset;
+		va = tex->buffer.gpu_address + tex->surface.fmask_offset;
 
 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
 		if (screen->info.chip_class == GFX9) {
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index ddef8da4e14..f2d0a10a843 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -449,23 +449,23 @@ void si_texture_discard_cmask(struct si_screen *sscreen,
 static bool si_can_disable_dcc(struct si_texture *tex)
 {
 	/* We can't disable DCC if it can be written by another process. */
-	return tex->dcc_offset &&
+	return tex->surface.dcc_offset &&
 	       (!tex->buffer.b.is_shared ||
 		!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE));
 }
 
 static void si_texture_zero_dcc_fields(struct si_texture *tex)
 {
-	tex->dcc_offset = 0;
-	tex->display_dcc_offset = 0;
-	tex->dcc_retile_map_offset = 0;
+	tex->surface.dcc_offset = 0;
+	tex->surface.display_dcc_offset = 0;
+	tex->surface.dcc_retile_map_offset = 0;
 }
 
 static bool si_texture_discard_dcc(struct si_screen *sscreen,
 				   struct si_texture *tex)
 {
 	if (!si_can_disable_dcc(tex)) {
-		assert(tex->display_dcc_offset == 0);
+		assert(tex->surface.display_dcc_offset == 0);
 		return false;
 	}
 
@@ -584,12 +584,11 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
 	tex->buffer.flags = new_tex->buffer.flags;
 
 	tex->surface = new_tex->surface;
-	tex->size = new_tex->size;
 	si_texture_reference(&tex->flushed_depth_texture,
 			     new_tex->flushed_depth_texture);
 
-	tex->fmask_offset = new_tex->fmask_offset;
-	tex->cmask_offset = new_tex->cmask_offset;
+	tex->surface.fmask_offset = new_tex->surface.fmask_offset;
+	tex->surface.cmask_offset = new_tex->surface.cmask_offset;
 	tex->cmask_base_address_reg = new_tex->cmask_base_address_reg;
 
 	if (tex->cmask_buffer == &tex->buffer)
@@ -602,13 +601,13 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
 	else
 		si_resource_reference(&tex->cmask_buffer, new_tex->cmask_buffer);
 
-	tex->dcc_offset = new_tex->dcc_offset;
+	tex->surface.dcc_offset = new_tex->surface.dcc_offset;
 	tex->cb_color_info = new_tex->cb_color_info;
 	memcpy(tex->color_clear_value, new_tex->color_clear_value,
 	       sizeof(tex->color_clear_value));
 	tex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
 
-	tex->htile_offset = new_tex->htile_offset;
+	tex->surface.htile_offset = new_tex->surface.htile_offset;
 	tex->depth_clear_value = new_tex->depth_clear_value;
 	tex->dirty_level_mask = new_tex->dirty_level_mask;
 	tex->stencil_dirty_level_mask = new_tex->stencil_dirty_level_mask;
@@ -630,10 +629,10 @@ static void si_reallocate_texture_inplace(struct si_context *sctx,
 				new_tex->last_dcc_separate_buffer);
 
 	if (new_bind_flag == PIPE_BIND_LINEAR) {
-		assert(!tex->htile_offset);
+		assert(!tex->surface.htile_offset);
 		assert(!tex->cmask_buffer);
 		assert(!tex->surface.fmask_size);
-		assert(!tex->dcc_offset);
+		assert(!tex->surface.dcc_offset);
 		assert(!tex->is_depth);
 	}
 
@@ -659,10 +658,10 @@ static void si_set_tex_bo_metadata(struct si_screen *sscreen,
 	if (sscreen->info.chip_class >= GFX9) {
 		md.u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
 
-		if (tex->dcc_offset && !tex->dcc_separate_buffer) {
+		if (tex->surface.dcc_offset && !tex->dcc_separate_buffer) {
 			uint64_t dcc_offset =
-				tex->display_dcc_offset ? tex->display_dcc_offset
-							: tex->dcc_offset;
+				tex->surface.display_dcc_offset ? tex->surface.display_dcc_offset
+							: tex->surface.dcc_offset;
 
 			assert((dcc_offset >> 8) != 0 && (dcc_offset >> 8) < (1 << 24));
 			md.u.gfx9.dcc_offset_256B = dcc_offset >> 8;
@@ -730,17 +729,17 @@ static void si_set_tex_bo_metadata(struct si_screen *sscreen,
 	case GFX7:
 		break;
 	case GFX8:
-		desc[7] = tex->dcc_offset >> 8;
+		desc[7] = tex->surface.dcc_offset >> 8;
 		break;
 	case GFX9:
-		desc[7] = tex->dcc_offset >> 8;
+		desc[7] = tex->surface.dcc_offset >> 8;
 		desc[5] &= C_008F24_META_DATA_ADDRESS;
-		desc[5] |= S_008F24_META_DATA_ADDRESS(tex->dcc_offset >> 40);
+		desc[5] |= S_008F24_META_DATA_ADDRESS(tex->surface.dcc_offset >> 40);
 		break;
 	case GFX10:
 		desc[6] &= C_00A018_META_DATA_ADDRESS_LO;
-		desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->dcc_offset >> 8);
-		desc[7] = tex->dcc_offset >> 16;
+		desc[6] |= S_00A018_META_DATA_ADDRESS_LO(tex->surface.dcc_offset >> 8);
+		desc[7] = tex->surface.dcc_offset >> 16;
 		break;
 	default:
 		assert(0);
@@ -814,11 +813,11 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
 		 */
 		switch (sscreen->info.chip_class) {
 		case GFX8:
-			tex->dcc_offset = (uint64_t)desc[7] << 8;
+			tex->surface.dcc_offset = (uint64_t)desc[7] << 8;
 			break;
 
 		case GFX9:
-			tex->dcc_offset =
+			tex->surface.dcc_offset =
 				((uint64_t)desc[7] << 8) |
 				((uint64_t)G_008F24_META_DATA_ADDRESS(desc[5]) << 40);
 			tex->surface.u.gfx9.dcc.pipe_aligned =
@@ -833,7 +832,7 @@ static bool si_read_tex_bo_metadata(struct si_screen *sscreen,
 			break;
 
 		case GFX10:
-			tex->dcc_offset =
+			tex->surface.dcc_offset =
 				((uint64_t)G_00A018_META_DATA_ADDRESS_LO(desc[6]) << 8) |
 				((uint64_t)desc[7] << 16);
 			tex->surface.u.gfx9.dcc.pipe_aligned =
@@ -865,14 +864,14 @@ static bool si_has_displayable_dcc(struct si_texture *tex)
 	 * (it can't be scanned out and rendered to simultaneously)
 	 */
 	if (sscreen->info.use_display_dcc_unaligned &&
-	    tex->dcc_offset &&
+	    tex->surface.dcc_offset &&
 	    !tex->surface.u.gfx9.dcc.pipe_aligned &&
 	    !tex->surface.u.gfx9.dcc.rb_aligned)
 		return true;
 
 	/* This needs an explicit flush (flush_resource). */
 	if (sscreen->info.use_display_dcc_with_retile_blit &&
-	    tex->display_dcc_offset)
+	    tex->surface.display_dcc_offset)
 		return true;
 
 	return false;
@@ -953,7 +952,7 @@ static bool si_texture_get_handle(struct pipe_screen* screen,
 		 * disable it for external clients that want write
 		 * access.
 		 */
-		if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->dcc_offset) ||
+		if ((usage & PIPE_HANDLE_USAGE_SHADER_WRITE && tex->surface.dcc_offset) ||
 		    /* Displayable DCC requires an explicit flush. */
 		    (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
 		     si_has_displayable_dcc(tex))) {
@@ -965,7 +964,7 @@ static bool si_texture_get_handle(struct pipe_screen* screen,
 		}
 
 		if (!(usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH) &&
-		    (tex->cmask_buffer || tex->dcc_offset)) {
+		    (tex->cmask_buffer || tex->surface.dcc_offset)) {
 			/* Eliminate fast clear (both CMASK and DCC) */
 			si_eliminate_fast_color_clear(sctx, tex);
 			/* eliminate_fast_color_clear flushes the context */
@@ -1095,10 +1094,10 @@ void si_print_texture_info(struct si_screen *sscreen,
 			tex->surface.u.gfx9.surf.epitch,
 			tex->surface.u.gfx9.surf_pitch);
 
-		if (tex->fmask_offset) {
+		if (tex->surface.fmask_offset) {
 			u_log_printf(log, "  FMASK: offset=%"PRIu64", size=%"PRIu64", "
 				"alignment=%u, swmode=%u, epitch=%u\n",
-				tex->fmask_offset,
+				tex->surface.fmask_offset,
 				tex->surface.fmask_size,
 				tex->surface.fmask_alignment,
 				tex->surface.u.gfx9.fmask.swizzle_mode,
@@ -1108,27 +1107,27 @@ void si_print_texture_info(struct si_screen *sscreen,
 		if (tex->cmask_buffer) {
 			u_log_printf(log, "  CMask: offset=%"PRIu64", size=%u, "
 				"alignment=%u, rb_aligned=%u, pipe_aligned=%u\n",
-				tex->cmask_offset,
+				tex->surface.cmask_offset,
 				tex->surface.cmask_size,
 				tex->surface.cmask_alignment,
 				tex->surface.u.gfx9.cmask.rb_aligned,
 				tex->surface.u.gfx9.cmask.pipe_aligned);
 		}
 
-		if (tex->htile_offset) {
+		if (tex->surface.htile_offset) {
 			u_log_printf(log, "  HTile: offset=%"PRIu64", size=%u, alignment=%u, "
 				"rb_aligned=%u, pipe_aligned=%u\n",
-				tex->htile_offset,
+				tex->surface.htile_offset,
 				tex->surface.htile_size,
 				tex->surface.htile_alignment,
 				tex->surface.u.gfx9.htile.rb_aligned,
 				tex->surface.u.gfx9.htile.pipe_aligned);
 		}
 
-		if (tex->dcc_offset) {
+		if (tex->surface.dcc_offset) {
 			u_log_printf(log, "  DCC: offset=%"PRIu64", size=%u, "
 				"alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
-				tex->dcc_offset, tex->surface.dcc_size,
+				tex->surface.dcc_offset, tex->surface.dcc_size,
 				tex->surface.dcc_alignment,
 				tex->surface.u.gfx9.display_dcc_pitch_max,
 				tex->surface.num_dcc_levels);
@@ -1150,10 +1149,10 @@ void si_print_texture_info(struct si_screen *sscreen,
 		tex->surface.u.legacy.tile_split, tex->surface.u.legacy.pipe_config,
 		(tex->surface.flags & RADEON_SURF_SCANOUT) != 0);
 
-	if (tex->fmask_offset)
+	if (tex->surface.fmask_offset)
 		u_log_printf(log, "  FMask: offset=%"PRIu64", size=%"PRIu64", alignment=%u, pitch_in_pixels=%u, "
 			"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
-			tex->fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,
+			tex->surface.fmask_offset, tex->surface.fmask_size, tex->surface.fmask_alignment,
 			tex->surface.u.legacy.fmask.pitch_in_pixels,
 			tex->surface.u.legacy.fmask.bankh,
 			tex->surface.u.legacy.fmask.slice_tile_max,
@@ -1162,19 +1161,19 @@ void si_print_texture_info(struct si_screen *sscreen,
 	if (tex->cmask_buffer)
 		u_log_printf(log, "  CMask: offset=%"PRIu64", size=%u, alignment=%u, "
 			"slice_tile_max=%u\n",
-			tex->cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment,
+			tex->surface.cmask_offset, tex->surface.cmask_size, tex->surface.cmask_alignment,
 			tex->surface.u.legacy.cmask_slice_tile_max);
 
-	if (tex->htile_offset)
+	if (tex->surface.htile_offset)
 		u_log_printf(log, "  HTile: offset=%"PRIu64", size=%u, "
 			"alignment=%u, TC_compatible = %u\n",
-			tex->htile_offset, tex->surface.htile_size,
+			tex->surface.htile_offset, tex->surface.htile_size,
 			tex->surface.htile_alignment,
 			tex->tc_compatible_htile);
 
-	if (tex->dcc_offset) {
+	if (tex->surface.dcc_offset) {
 		u_log_printf(log, "  DCC: offset=%"PRIu64", size=%u, alignment=%u\n",
-			tex->dcc_offset, tex->surface.dcc_size,
+			tex->surface.dcc_offset, tex->surface.dcc_size,
 			tex->surface.dcc_alignment);
 		for (i = 0; i <= tex->buffer.b.b.last_level; i++)
 			u_log_printf(log, "  DCCLevel[%i]: enabled=%u, offset=%u, "
@@ -1273,15 +1272,6 @@ si_texture_create_object(struct pipe_screen *screen,
 	 */
 	tex->ps_draw_ratio = 0;
 
-	/* TODO: remove these */
-	tex->fmask_offset = tex->surface.fmask_offset;
-	tex->cmask_offset = tex->surface.cmask_offset;
-	tex->htile_offset = tex->surface.htile_offset;
-	tex->dcc_offset = tex->surface.dcc_offset;
-	tex->display_dcc_offset = tex->surface.display_dcc_offset;
-	tex->dcc_retile_map_offset = tex->surface.dcc_retile_map_offset;
-	tex->size = tex->surface.total_size;
-
 	if (tex->is_depth) {
 		if (sscreen->info.chip_class >= GFX9) {
 			tex->can_sample_z = true;
@@ -1309,7 +1299,7 @@ si_texture_create_object(struct pipe_screen *screen,
 
 	/* Now create the backing buffer. */
 	if (!buf) {
-		si_init_resource_fields(sscreen, resource, tex->size,
+		si_init_resource_fields(sscreen, resource, tex->surface.total_size,
 					  tex->surface.surf_alignment);
 
 		if (!si_alloc_resource(sscreen, resource))
@@ -1329,23 +1319,23 @@ si_texture_create_object(struct pipe_screen *screen,
 	if (tex->cmask_buffer) {
 		/* Initialize the cmask to 0xCC (= compressed state). */
 		si_screen_clear_buffer(sscreen, &tex->cmask_buffer->b.b,
-					 tex->cmask_offset, tex->surface.cmask_size,
+					 tex->surface.cmask_offset, tex->surface.cmask_size,
 					 0xCCCCCCCC);
 	}
-	if (tex->htile_offset) {
+	if (tex->surface.htile_offset) {
 		uint32_t clear_value = 0;
 
 		if (sscreen->info.chip_class >= GFX9 || tex->tc_compatible_htile)
 			clear_value = 0x0000030F;
 
 		si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
-					 tex->htile_offset,
+					 tex->surface.htile_offset,
 					 tex->surface.htile_size,
 					 clear_value);
 	}
 
 	/* Initialize DCC only if the texture is not being imported. */
-	if (!buf && tex->dcc_offset) {
+	if (!buf && tex->surface.dcc_offset) {
 		/* Clear DCC to black for all tiles with DCC enabled.
 		 *
 		 * This fixes corruption in 3DMark Slingshot Extreme, which
@@ -1355,13 +1345,13 @@ si_texture_create_object(struct pipe_screen *screen,
 		    tex->buffer.b.b.nr_samples <= 2) {
 			/* Simple case - all tiles have DCC enabled. */
 			si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
-					       tex->dcc_offset,
+					       tex->surface.dcc_offset,
 					       tex->surface.dcc_size,
 					       DCC_CLEAR_COLOR_0000);
 		} else if (sscreen->info.chip_class >= GFX9) {
 			/* Clear to uncompressed. Clearing this to black is complicated. */
 			si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
-					       tex->dcc_offset,
+					       tex->surface.dcc_offset,
 					       tex->surface.dcc_size,
 					       DCC_UNCOMPRESSED);
 		} else {
@@ -1369,7 +1359,7 @@ si_texture_create_object(struct pipe_screen *screen,
 			if (tex->buffer.b.b.nr_samples >= 2) {
 				/* Clearing this to black is complicated. */
 				si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
-						       tex->dcc_offset,
+						       tex->surface.dcc_offset,
 						       tex->surface.dcc_size,
 						       DCC_UNCOMPRESSED);
 			} else {
@@ -1387,13 +1377,13 @@ si_texture_create_object(struct pipe_screen *screen,
 				/* Mipmap levels with DCC. */
 				if (size) {
 					si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
-							       tex->dcc_offset, size,
+							       tex->surface.dcc_offset, size,
 							       DCC_CLEAR_COLOR_0000);
 				}
 				/* Mipmap levels without DCC. */
 				if (size != tex->surface.dcc_size) {
 					si_screen_clear_buffer(sscreen, &tex->buffer.b.b,
-							       tex->dcc_offset + size,
+							       tex->surface.dcc_offset + size,
 							       tex->surface.dcc_size - size,
 							       DCC_UNCOMPRESSED);
 				}
@@ -1401,7 +1391,7 @@ si_texture_create_object(struct pipe_screen *screen,
 		}
 
 		/* Upload the DCC retile map. */
-		if (tex->dcc_retile_map_offset) {
+		if (tex->surface.dcc_retile_map_offset) {
 			/* Use a staging buffer for the upload, because
 			 * the buffer backing the texture is unmappable.
 			 */
@@ -1429,10 +1419,10 @@ si_texture_create_object(struct pipe_screen *screen,
 			struct pipe_box box;
 			u_box_1d(0, buf->b.b.width0, &box);
 
-			assert(tex->dcc_retile_map_offset <= UINT_MAX);
+			assert(tex->surface.dcc_retile_map_offset <= UINT_MAX);
 			mtx_lock(&sscreen->aux_context_lock);
 			sctx->dma_copy(&sctx->b, &tex->buffer.b.b, 0,
-				       tex->dcc_retile_map_offset, 0, 0,
+				       tex->surface.dcc_retile_map_offset, 0, 0,
 				       &buf->b.b, 0, &box);
 			sscreen->aux_context->flush(sscreen->aux_context, NULL, 0);
 			mtx_unlock(&sscreen->aux_context_lock);
@@ -1443,7 +1433,7 @@ si_texture_create_object(struct pipe_screen *screen,
 
 	/* Initialize the CMASK base register value. */
 	tex->cmask_base_address_reg =
-		(tex->buffer.gpu_address + tex->cmask_offset) >> 8;
+		(tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
 
 	if (sscreen->debug_flags & DBG(VM)) {
 		fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Texture %ix%ix%i, %i levels, %i samples, %s\n",
@@ -1829,11 +1819,11 @@ static void si_texture_invalidate_storage(struct si_context *sctx,
 
 	/* Initialize the CMASK base address (needed even without CMASK). */
 	tex->cmask_base_address_reg =
-		(tex->buffer.gpu_address + tex->cmask_offset) >> 8;
+		(tex->buffer.gpu_address + tex->surface.cmask_offset) >> 8;
 
 	p_atomic_inc(&sscreen->dirty_tex_counter);
 
-	sctx->num_alloc_tex_transfer_bytes += tex->size;
+	sctx->num_alloc_tex_transfer_bytes += tex->surface.total_size;
 }
 
 static void *si_texture_transfer_map(struct pipe_context *ctx,
@@ -2391,7 +2381,7 @@ void vi_separate_dcc_try_enable(struct si_context *sctx,
 
 	assert(sctx->chip_class >= GFX8);
 
-	if (tex->dcc_offset)
+	if (tex->surface.dcc_offset)
 		return; /* already enabled */
 
 	/* Enable the DCC stat gathering. */
@@ -2426,7 +2416,7 @@ void vi_separate_dcc_try_enable(struct si_context *sctx,
 	}
 
 	/* dcc_offset is the absolute GPUVM address. */
-	tex->dcc_offset = tex->dcc_separate_buffer->gpu_address;
+	tex->surface.dcc_offset = tex->dcc_separate_buffer->gpu_address;
 
 	/* no need to flag anything since this is called by fast clear that
 	 * flags framebuffer state
@@ -2485,7 +2475,7 @@ void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
 		assert(!tex->last_dcc_separate_buffer);
 		tex->last_dcc_separate_buffer = tex->dcc_separate_buffer;
 		tex->dcc_separate_buffer = NULL;
-		tex->dcc_offset = 0;
+		tex->surface.dcc_offset = 0;
 		/* no need to flag anything since this is called after
 		 * decompression that re-sets framebuffer state
 		 */