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authorAlex Deucher <[email protected]>2011-06-22 12:33:01 -0400
committerAlex Deucher <[email protected]>2011-06-22 12:34:37 -0400
commitc4930cb417defe9f58c27e909adb18d3c7784883 (patch)
treec2264e2e5da5fd0a430411d0b98025bcf2268a4f /src
parenteb2c9b5814f7c6a5b37bc9063b1593095ea4f620 (diff)
r600g: fix num_banks interpretation on eg+
Field is encoded: 0 = 4 banks 1 = 8 banks 2 = 16 banks Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/winsys/r600/drm/r600_drm.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c b/src/gallium/winsys/r600/drm/r600_drm.c
index 03fe385334c..4602f7f2a4b 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -156,7 +156,20 @@ static int eg_interpret_tiling(struct radeon *radeon, uint32_t tiling_config)
return -EINVAL;
}
- radeon->tiling_info.num_banks = (tiling_config & 0xf0) >> 4;
+ switch ((tiling_config & 0xf0) >> 4) {
+ case 0:
+ radeon->tiling_info.num_banks = 4;
+ break;
+ case 1:
+ radeon->tiling_info.num_banks = 8;
+ break;
+ case 2:
+ radeon->tiling_info.num_banks = 16;
+ break;
+ default:
+ return -EINVAL;
+
+ }
switch ((tiling_config & 0xf00) >> 8) {
case 0: