diff options
| author | Samuel Pitoiset <[email protected]> | 2016-02-14 00:14:34 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2016-02-16 21:39:00 +0100 |
| commit | bc331dd8389312cbb2f1bac323e7cd79b155cfa0 (patch) | |
| tree | 4c7a2dbffb14a08d89178dc0456f9e203e1227ba /src | |
| parent | a61823b584d75dddf46061135b08b2777a8c468d (diff) | |
nvc0: fix compute state initialization on GK110+
Because our firmware doesn't support the GK110_COMPUTE.FIRMWARE[0x6]
method the GPU hangs when it is used. Removing it fix the issue and
allow to launch compute shaders on GK110+.
Tested on GK208 and GM107.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Ilia Mirkin <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/nouveau/nvc0/nve4_compute.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c index 1719e091c53..ac31aae0a73 100644 --- a/src/gallium/drivers/nouveau/nvc0/nve4_compute.c +++ b/src/gallium/drivers/nouveau/nvc0/nve4_compute.c @@ -39,7 +39,7 @@ nve4_screen_compute_setup(struct nvc0_screen *screen, { struct nouveau_device *dev = screen->base.device; struct nouveau_object *chan = screen->base.channel; - unsigned i; + int i; int ret; uint32_t obj_class; @@ -115,13 +115,14 @@ nve4_screen_compute_setup(struct nvc0_screen *screen, PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1); if (obj_class >= NVF0_COMPUTE_CLASS) { - BEGIN_NVC0(push, SUBC_COMPUTE(0x0248), 1); - PUSH_DATA (push, 0x100); - BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 63); - for (i = 63; i >= 1; --i) + /* The blob calls GK110_COMPUTE.FIRMWARE[0x6], along with the args (0x1) + * passed with GK110_COMPUTE.GRAPH.SCRATCH[0x2]. This is currently + * disabled because our firmware doesn't support these commands and the + * GPU hangs if they are used. */ + BEGIN_NIC0(push, SUBC_COMPUTE(0x0248), 64); + for (i = 63; i >= 0; i--) PUSH_DATA(push, 0x38000 | i); IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0); - IMMED_NVC0(push, SUBC_COMPUTE(0x518), 0); } BEGIN_NVC0(push, NVE4_COMPUTE(TEX_CB_INDEX), 1); |