diff options
| author | Eric Anholt <[email protected]> | 2017-10-24 09:53:32 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2017-10-30 13:31:15 -0700 |
| commit | bacbcafec16c1ff106aa8c01f70d6eea28c5ac79 (patch) | |
| tree | 12fb03aee2498a8511b19d7c73907eca9559f6e6 /src | |
| parent | 443e1984d2ce42580856489a0adb987f6af64786 (diff) | |
broadcom/vc5: Always set up 1D textures as raster order.
1D is the exception to "all V3D textures are tiled", since tiling 1D
textures would just waste memory and cache space. This ended up being a
problem once we started actually marking 1D textures as 1D instead of 2D.
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/vc5/vc5_resource.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/gallium/drivers/vc5/vc5_resource.c b/src/gallium/drivers/vc5/vc5_resource.c index 42d58791f6c..45f94af0346 100644 --- a/src/gallium/drivers/vc5/vc5_resource.c +++ b/src/gallium/drivers/vc5/vc5_resource.c @@ -526,6 +526,11 @@ vc5_resource_create_with_modifiers(struct pipe_screen *pscreen, if (tmpl->bind & (PIPE_BIND_LINEAR | PIPE_BIND_CURSOR)) should_tile = false; + /* 1D and 1D_ARRAY textures are always raster-order. */ + if (tmpl->target == PIPE_TEXTURE_1D || + tmpl->target == PIPE_TEXTURE_1D_ARRAY) + should_tile = false; + /* Scanout BOs for simulator need to be linear for interaction with * i965. */ |