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authorMarek Olšák <marek.olsak@amd.com>2014-08-20 23:58:24 +0200
committerMarek Olšák <marek.olsak@amd.com>2014-09-01 21:18:49 +0200
commitba14d4910c946aeba39b43ac0dce9c2a76f49b30 (patch)
tree1c990b243a534e499c9c4a049bb7c4a1350d0d8b /src
parent13b93596daebb5c871b786521093586cf9f0fe31 (diff)
r600g: set VGT_ENHANCE=4 on R7xx
This is a golden setting on RV740, but there is a hw bug which recommends setting it on all R7xx chipsets. Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/r600/r600_state.c1
-rw-r--r--src/gallium/drivers/r600/r600d.h1
2 files changed, 2 insertions, 0 deletions
diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c
index 3d1700f5300..36f77503141 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2272,6 +2272,7 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
if (rctx->b.chip_class >= R700) {
+ r600_store_context_reg(cb, R_028A50_VGT_ENHANCE, 4);
r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 17568abd05b..3cf7b8800f4 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -889,6 +889,7 @@
#define S_028A40_CUT_MODE(x) (((x) & 0x3) << 3)
#define G_028A40_CUT_MODE(x) (((x) >> 3) & 0x3)
#define C_028A40_CUT_MODE 0xFFFFFFE7
+#define R_028A50_VGT_ENHANCE 0x028A50
#define R_028A6C_VGT_GS_OUT_PRIM_TYPE 0x028A6C
#define S_028A6C_OUTPRIM_TYPE(x) (((x) & 0x3F) << 0)
#define V_028A6C_OUTPRIM_TYPE_POINTLIST 0