diff options
| author | Jose Maria Casanova Crespo <[email protected]> | 2019-07-24 22:01:00 +0200 |
|---|---|---|
| committer | Jose Maria Casanova Crespo <[email protected]> | 2019-09-05 22:54:13 +0100 |
| commit | a5df0fa0b1d821a3d3f6f483b0c712aff3dad364 (patch) | |
| tree | e3c0d353423c9468be1a872ef85938375cbb78bd /src | |
| parent | 1dce75c1839f08cfa78400367019f998c258eff5 (diff) | |
v3d: writes to magic registers aren't RF writes after THREND
Shaders must not attempt to write to the register files in the last
three instructions, but that doesn't include the magic registers:
nop ; nop ; thrsw; ldtmu.- *** ERROR ***
nop ; nop
nop ; nop
v2: Simplify validation rules. (Eric Anholt)
v3: Adjust validation even more. (Eric Anholt)
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/broadcom/compiler/qpu_validate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/broadcom/compiler/qpu_validate.c b/src/broadcom/compiler/qpu_validate.c index fb2ed123aba..24be4fd39e5 100644 --- a/src/broadcom/compiler/qpu_validate.c +++ b/src/broadcom/compiler/qpu_validate.c @@ -258,8 +258,10 @@ qpu_validate_inst(struct v3d_qpu_validate_state *state, struct qinst *qinst) fail_instr(state, "RF write after THREND"); } - if (v3d_qpu_sig_writes_address(devinfo, &inst->sig)) + if (v3d_qpu_sig_writes_address(devinfo, &inst->sig) && + !inst->sig_magic) { fail_instr(state, "RF write after THREND"); + } /* GFXH-1625: No TMUWT in the last instruction */ if (state->last_thrsw_ip - state->ip == 2 && |