diff options
| author | Kenneth Graunke <[email protected]> | 2011-08-12 18:27:16 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-01-28 17:08:28 -0800 |
| commit | 9add4e803877f97ad7f6d479d81d537426f09b6f (patch) | |
| tree | bb2139dc30b018c2a50d4eab969f8303c2ee20bb /src | |
| parent | 7b07808f741ea31831a953aad58749b75a12a108 (diff) | |
i965: Add chipset limits for Haswell GT1/GT2.
The maximum number of URB entries come from the 3DSTATE_URB_VS and
3DSTATE_URB_GS state packet documentation; the thread count information
comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Kenneth Graunke <[email protected]>
Signed-off-by: Eugeni Dodonov <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 1201565745d..9b9d3103b49 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -278,7 +278,23 @@ brwCreateContext(int api, } /* WM maximum threads is number of EUs times number of threads per EU. */ - if (intel->gen >= 7) { + assert(intel->gen <= 7); + + if (intel->is_haswell) { + if (intel->gt == 1) { + brw->max_wm_threads = 102; + brw->max_vs_threads = 70; + brw->urb.size = 128; + brw->urb.max_vs_entries = 640; + brw->urb.max_gs_entries = 256; + } else if (intel->gt == 2) { + brw->max_wm_threads = 204; + brw->max_vs_threads = 280; + brw->urb.size = 256; + brw->urb.max_vs_entries = 1664; + brw->urb.max_gs_entries = 640; + } + } else if (intel->gen == 7) { if (intel->gt == 1) { brw->max_wm_threads = 48; brw->max_vs_threads = 36; |