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authorLucas Stach <[email protected]>2018-02-22 11:54:21 +0100
committerLucas Stach <[email protected]>2019-10-18 19:06:39 +0200
commit95adc393eb4235c29696a4ad6244ad8d710db524 (patch)
tree97928156a78fc7b183ae6730b0702019104a74e5 /src
parent54dd288317ddd2c5ef719043c1fd0942eb33d7dc (diff)
etnaviv: GC7000: flush TX descriptor and instruction cache
The etnaviv kernel driver will only ever flush write caches. As both the TX descriptor and instruction cache are read caches they must be flushed from the user cmdstream at an appropriate time. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/etnaviv/etnaviv_context.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c b/src/gallium/drivers/etnaviv/etnaviv_context.c
index fec4f3958e7..367f31f2e9b 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -413,9 +413,16 @@ static void etna_reset_gpu_state(struct etna_context *ctx)
* before command stream submission. It does not need flushing if the
* referenced image data changes.
*/
+ etna_set_state(stream, VIVS_NTE_DESCRIPTOR_FLUSH, 0);
etna_set_state(stream, VIVS_GL_FLUSH_CACHE,
VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 |
VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13);
+
+ /* Icache invalidate (should do this on shader change?) */
+ etna_set_state(stream, VIVS_VS_ICACHE_INVALIDATE,
+ VIVS_VS_ICACHE_INVALIDATE_UNK0 | VIVS_VS_ICACHE_INVALIDATE_UNK1 |
+ VIVS_VS_ICACHE_INVALIDATE_UNK2 | VIVS_VS_ICACHE_INVALIDATE_UNK3 |
+ VIVS_VS_ICACHE_INVALIDATE_UNK4);
}
ctx->dirty = ~0L;