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authorMarek Olšák <[email protected]>2016-04-22 10:18:17 +0200
committerMarek Olšák <[email protected]>2016-04-28 12:46:47 +0200
commit7e7710a068a7c1e9095eb8e718c56d925d2f0164 (patch)
tree5aaea257180e9e8103f9236a8a27cb2298df6ba3 /src
parent7d49b459b64e8cad2210c2ffc409b4efe6ea2214 (diff)
radeonsi: remove needless cache flushes at the end of CP DMA operations
not needed AFAIK Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/radeonsi/si_cp_dma.c8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c b/src/gallium/drivers/radeonsi/si_cp_dma.c
index 38e0ee60d64..bca9cc5020e 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -206,10 +206,6 @@ static void si_clear_buffer(struct pipe_context *ctx, struct pipe_resource *dst,
va += byte_count;
}
- /* Flush the caches again in case the 3D engine has been prefetching
- * the resource. */
- sctx->b.flags |= flush_flags;
-
if (tc_l2_flag)
r600_resource(dst)->TC_L2_dirty = true;
}
@@ -336,10 +332,6 @@ void si_copy_buffer(struct si_context *sctx,
if (realign_size)
si_cp_dma_realign_engine(sctx, realign_size);
- /* Flush the caches again in case the 3D engine has been prefetching
- * the resource. */
- sctx->b.flags |= flush_flags;
-
if (tc_l2_flag)
r600_resource(dst)->TC_L2_dirty = true;
}