diff options
| author | Marek Olšák <[email protected]> | 2016-04-17 15:52:55 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-04-18 19:51:25 +0200 |
| commit | 78f58a4e6fe854378958223d4103fca09e58fbd7 (patch) | |
| tree | 075204aa9e505a323422deaa99dce28daf3ed46e /src | |
| parent | 3faecdd4e13a773e188d7b1c7647e61ee0aa50bb (diff) | |
radeonsi: don't use ACQUIRE_MEM on the graphics ring
It's only required on the compute ring. This matches the closed driver.
The compute flag is removed to prevent confusion and Bas's compute shader
patches remove it in the whole function.
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_state_draw.c | 26 |
1 files changed, 8 insertions, 18 deletions
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 8f4eba4151e..86fb4431022 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -699,26 +699,16 @@ void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom) radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); } - /* SURFACE_SYNC must be emitted after partial flushes. - * It looks like SURFACE_SYNC flushes caches immediately and doesn't - * wait for any engines. This should be last. + /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle. + * Therefore, it should be last. */ if (cp_coher_cntl) { - if (sctx->chip_class >= CIK) { - radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0) | compute); - radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ - radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ - radeon_emit(cs, 0xff); /* CP_COHER_SIZE_HI */ - radeon_emit(cs, 0); /* CP_COHER_BASE */ - radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ - radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ - } else { - radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0) | compute); - radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ - radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ - radeon_emit(cs, 0); /* CP_COHER_BASE */ - radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ - } + /* ACQUIRE_MEM is only required on a compute ring. */ + radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0)); + radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ + radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ + radeon_emit(cs, 0); /* CP_COHER_BASE */ + radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ } if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) { |