diff options
| author | [email protected] <[email protected]> | 2018-06-04 09:03:37 -0700 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2018-06-05 14:28:49 +1000 |
| commit | 6ce94a50bbe2bfc0f5dfb58d39f5ddfece7a3320 (patch) | |
| tree | 3826b51e2dd5b3176b3644a5bed123a1c02e1a9e /src | |
| parent | 1c9053d0765dc6372238e333dc5adca3e175b210 (diff) | |
virgl: add shader offset alignment to to v2 caps struct
This is the SSBO analogue to fe0647. User supplied data must
be a multiple of GL_SHADER_STORAGE_BUFFER_OFFSET_ALIGNMENT.
This fixes 44 GLES31 tests on airlied@'s GLES31 sketch branches with
Nvidia hardware, but this patch standalone can applied to master. The
alignment restriction on Nvidia is 32, hence the default value.
Example tests:
dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.0
dEQP-GLES31.functional.ssbo.layout.multi_basic_types.single_buffer.std430
v2: Move to a better place in case statement
v3: Rebase
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/virgl/virgl_hw.h | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/virgl/virgl_screen.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/virgl/virgl_winsys.h | 1 |
3 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/virgl/virgl_hw.h b/src/gallium/drivers/virgl/virgl_hw.h index 261b690f533..a2c70bf86b6 100644 --- a/src/gallium/drivers/virgl/virgl_hw.h +++ b/src/gallium/drivers/virgl/virgl_hw.h @@ -292,6 +292,7 @@ struct virgl_caps_v2 { int32_t max_texture_gather_offset; uint32_t texture_buffer_offset_alignment; uint32_t uniform_buffer_offset_alignment; + uint32_t shader_buffer_offset_alignment; }; union virgl_caps { diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index b5f5d9921af..e8d1c751779 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -211,6 +211,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param) return vscreen->caps.caps.v1.bset.polygon_offset_clamp; case PIPE_CAP_QUERY_SO_OVERFLOW: return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query; + case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: + return vscreen->caps.caps.v2.shader_buffer_offset_alignment; case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: case PIPE_CAP_FAKE_SW_MSAA: @@ -236,7 +238,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_TGSI_PACK_HALF_FLOAT: case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: - case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_INVALIDATE_BUFFER: case PIPE_CAP_GENERATE_MIPMAP: case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: diff --git a/src/gallium/drivers/virgl/virgl_winsys.h b/src/gallium/drivers/virgl/virgl_winsys.h index 690e610e199..83cb93138aa 100644 --- a/src/gallium/drivers/virgl/virgl_winsys.h +++ b/src/gallium/drivers/virgl/virgl_winsys.h @@ -134,5 +134,6 @@ static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps) caps->caps.v2.max_texture_gather_offset = 7; caps->caps.v2.texture_buffer_offset_alignment = 0; caps->caps.v2.uniform_buffer_offset_alignment = 256; + caps->caps.v2.shader_buffer_offset_alignment = 32; } #endif |