diff options
| author | Kenneth Graunke <[email protected]> | 2019-01-17 23:44:09 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2019-02-21 10:26:11 -0800 |
| commit | 61798e3c88f299d14a084c10cfefa9d6679f0505 (patch) | |
| tree | 1471b47888deeac2103627034f8f76da4e0b2d43 /src | |
| parent | c81941f1e7d72b80450e2250dcc1537177fd82c8 (diff) | |
iris: CS stall on VF cache invalidate workarounds
See commit 31e4c9ce400341df9b0136419b3b3c73b8c9eb7e in i965.
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/iris/iris_blorp.c | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/iris/iris_state.c | 6 |
2 files changed, 6 insertions, 3 deletions
diff --git a/src/gallium/drivers/iris/iris_blorp.c b/src/gallium/drivers/iris/iris_blorp.c index cd5f919bdca..c372c7f6be5 100644 --- a/src/gallium/drivers/iris/iris_blorp.c +++ b/src/gallium/drivers/iris/iris_blorp.c @@ -216,7 +216,8 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *blorp_batch, } if (need_invalidate) { - iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE); + iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE | + PIPE_CONTROL_CS_STALL); } } diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 49075418d3b..999edfd10e4 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -4546,7 +4546,8 @@ iris_upload_dirty_render_state(struct iris_context *ice, high_bits = res->bo->gtt_offset >> 32ull; if (high_bits != ice->state.last_vbo_high_bits[i]) { - flush_flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; + flush_flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE | + PIPE_CONTROL_CS_STALL; ice->state.last_vbo_high_bits[i] = high_bits; } @@ -4671,7 +4672,8 @@ iris_upload_render_state(struct iris_context *ice, /* The VF cache key only uses 32-bits, see vertex buffer comment above */ uint16_t high_bits = bo->gtt_offset >> 32ull; if (high_bits != ice->state.last_index_bo_high_bits) { - iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE); + iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE | + PIPE_CONTROL_CS_STALL); ice->state.last_index_bo_high_bits = high_bits; } } |