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authorSamuel Pitoiset <[email protected]>2019-06-25 12:16:39 +0200
committerBas Nieuwenhuizen <[email protected]>2019-07-07 17:03:39 +0200
commit4c31f3dcc021a4e317f35f29442742320b86cd20 (patch)
tree9f1895b50c117ce2882c3bd8f453907c4bea65aa /src
parent8574a842918e564ee250a736e2234ad29c8c023e (diff)
radv/gfx10: fix PS exports for SPI_SHADER_32_AR
Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/amd/vulkan/radv_nir_to_llvm.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index bf5571f30c7..84ab586caac 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2596,9 +2596,15 @@ si_llvm_init_export_args(struct radv_shader_context *ctx,
break;
case V_028714_SPI_SHADER_32_AR:
- args->enabled_channels = 0x9;
- args->out[0] = values[0];
- args->out[3] = values[3];
+ if (ctx->ac.chip_class >= GFX10) {
+ args->enabled_channels = 0x3;
+ args->out[0] = values[0];
+ args->out[1] = values[3];
+ } else {
+ args->enabled_channels = 0x9;
+ args->out[0] = values[0];
+ args->out[3] = values[3];
+ }
break;
case V_028714_SPI_SHADER_FP16_ABGR: