diff options
| author | Ian Romanick <[email protected]> | 2018-09-21 00:35:18 -0700 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-23 00:18:57 +0000 |
| commit | 44471a76e9b32410d02c202c67ce48a3b69770a8 (patch) | |
| tree | 881315e72c5b3ab37706270963235d4b9daea1e7 /src | |
| parent | de6c0f848797d26d28223bcad25da03654461874 (diff) | |
nir/spirv: Translate SPIR-V to NIR for new INTEL_shader_integer_functions2 opcodes
v2: Rebase on 272e927d0e9 ("nir/spirv: initial handling of OpenCL.std
extension opcodes")
v3: Add missing SpvOpUCountTrailingZerosINTEL case to switch in
vtn_handle_body_instruction. Remove stray semicolon in
vtn_nir_alu_op_for_spirv_opcode. Use umin instead of umax for
SpvOpUCountTrailingZerosINTEL "lowering" in vtn_handle_alu.
Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/767>
Diffstat (limited to 'src')
| -rw-r--r-- | src/compiler/spirv/spirv_to_nir.c | 14 | ||||
| -rw-r--r-- | src/compiler/spirv/vtn_alu.c | 21 |
2 files changed, 35 insertions, 0 deletions
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index dd53cee3be6..145e0e25fbd 100644 --- a/src/compiler/spirv/spirv_to_nir.c +++ b/src/compiler/spirv/spirv_to_nir.c @@ -4925,6 +4925,20 @@ vtn_handle_body_instruction(struct vtn_builder *b, SpvOp opcode, case SpvOpVectorTimesMatrix: case SpvOpMatrixTimesVector: case SpvOpMatrixTimesMatrix: + case SpvOpUCountLeadingZerosINTEL: + case SpvOpUCountTrailingZerosINTEL: + case SpvOpAbsISubINTEL: + case SpvOpAbsUSubINTEL: + case SpvOpIAddSatINTEL: + case SpvOpUAddSatINTEL: + case SpvOpIAverageINTEL: + case SpvOpUAverageINTEL: + case SpvOpIAverageRoundedINTEL: + case SpvOpUAverageRoundedINTEL: + case SpvOpISubSatINTEL: + case SpvOpUSubSatINTEL: + case SpvOpIMul32x16INTEL: + case SpvOpUMul32x16INTEL: vtn_handle_alu(b, opcode, w, count); break; diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index f60d7cddafc..fc3fb3c4d68 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -261,6 +261,21 @@ vtn_nir_alu_op_for_spirv_opcode(struct vtn_builder *b, case SpvOpBitReverse: return nir_op_bitfield_reverse; case SpvOpBitCount: return nir_op_bit_count; + case SpvOpUCountLeadingZerosINTEL: return nir_op_uclz; + /* SpvOpUCountTrailingZerosINTEL is handled elsewhere. */ + case SpvOpAbsISubINTEL: return nir_op_uabs_isub; + case SpvOpAbsUSubINTEL: return nir_op_uabs_usub; + case SpvOpIAddSatINTEL: return nir_op_iadd_sat; + case SpvOpUAddSatINTEL: return nir_op_uadd_sat; + case SpvOpIAverageINTEL: return nir_op_ihadd; + case SpvOpUAverageINTEL: return nir_op_uhadd; + case SpvOpIAverageRoundedINTEL: return nir_op_irhadd; + case SpvOpUAverageRoundedINTEL: return nir_op_urhadd; + case SpvOpISubSatINTEL: return nir_op_isub_sat; + case SpvOpUSubSatINTEL: return nir_op_usub_sat; + case SpvOpIMul32x16INTEL: return nir_op_imul_32x16; + case SpvOpUMul32x16INTEL: return nir_op_umul_32x16; + /* The ordered / unordered operators need special implementation besides * the logical operator to use since they also need to check if operands are * ordered. @@ -640,6 +655,12 @@ vtn_handle_alu(struct vtn_builder *b, SpvOp opcode, break; } + case SpvOpUCountTrailingZerosINTEL: + val->ssa->def = nir_umin(&b->nb, + nir_find_lsb(&b->nb, src[0]), + nir_imm_int(&b->nb, 32u)); + break; + default: { bool swap; unsigned src_bit_size = glsl_get_bit_size(vtn_src[0]->type); |