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authorJason Ekstrand <[email protected]>2016-06-01 18:55:35 -0700
committerJason Ekstrand <[email protected]>2016-06-03 19:29:28 -0700
commit35bf4d9dc2ba729469f2805984482d63b1aa8b8f (patch)
treec7b812410f1b1c7981cd2aa83c10c2e4cb568daa /src
parent3fb289f957a8a27349a6f7df03983f92d9b6cf64 (diff)
i965/ps_state: Use wm_prog_data.has_side_effects
Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_state.c8
-rw-r--r--src/mesa/drivers/dri/i965/gen8_ps_state.c7
2 files changed, 6 insertions, 9 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index a618c3ed87b..8d4d4fc6069 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -78,10 +78,8 @@ upload_wm_state(struct brw_context *brw)
}
/* _NEW_BUFFERS | _NEW_COLOR */
- const bool active_fs_has_side_effects =
- _mesa_active_fragment_shader_has_side_effects(&brw->ctx);
if (brw_color_buffer_write_enabled(brw) || writes_depth ||
- active_fs_has_side_effects || dw1 & GEN7_WM_KILL_ENABLE) {
+ prog_data->has_side_effects || dw1 & GEN7_WM_KILL_ENABLE) {
dw1 |= GEN7_WM_DISPATCH_ENABLE;
}
if (multisampled_fbo) {
@@ -107,7 +105,7 @@ upload_wm_state(struct brw_context *brw)
/* BRW_NEW_FS_PROG_DATA */
if (prog_data->early_fragment_tests)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
- else if (active_fs_has_side_effects)
+ else if (prog_data->has_side_effects)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
/* The "UAV access enable" bits are unnecessary on HSW because they only
@@ -120,7 +118,7 @@ upload_wm_state(struct brw_context *brw)
*/
if (brw->is_haswell &&
!(brw_color_buffer_write_enabled(brw) || writes_depth) &&
- active_fs_has_side_effects)
+ prog_data->has_side_effects)
dw2 |= HSW_WM_UAV_ONLY;
BEGIN_BATCH(3);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index c475a52afe0..51a3121c723 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -32,7 +32,6 @@ void
gen8_upload_ps_extra(struct brw_context *brw,
const struct brw_wm_prog_data *prog_data)
{
- struct gl_context *ctx = &brw->ctx;
uint32_t dw1 = 0;
dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
@@ -95,8 +94,8 @@ gen8_upload_ps_extra(struct brw_context *brw,
*
* BRW_NEW_FS_PROG_DATA | BRW_NEW_FRAGMENT_PROGRAM | _NEW_BUFFERS | _NEW_COLOR
*/
- if ((_mesa_active_fragment_shader_has_side_effects(ctx) ||
- prog_data->uses_kill) && !brw_color_buffer_write_enabled(brw))
+ if ((prog_data->has_side_effects || prog_data->uses_kill) &&
+ !brw_color_buffer_write_enabled(brw))
dw1 |= GEN8_PSX_SHADER_HAS_UAV;
if (prog_data->computed_stencil) {
@@ -155,7 +154,7 @@ upload_wm_state(struct brw_context *brw)
/* BRW_NEW_FS_PROG_DATA */
if (brw->wm.prog_data->early_fragment_tests)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PREPS;
- else if (_mesa_active_fragment_shader_has_side_effects(&brw->ctx))
+ else if (brw->wm.prog_data->has_side_effects)
dw1 |= GEN7_WM_EARLY_DS_CONTROL_PSEXEC;
BEGIN_BATCH(2);